A 0.9 V Low-power 16-bit DSP Based on a Top-down Design Methodology

A 0.9 V low-power (8.7 mW) 16-bit DSP was developed for mobile wireless use using a 0.25 µm dual-threshold-voltage (dual-Vth) CMOS process. To obtain a high-performance LSI at a low supply voltage and also to speed up the design process, we propose a new top-down design methodology in which iterations are done within the block synthesis step so that the layout can be fixed in one pass. There are four main design steps in the methodology. 1) Inter-block wires in the chip top level are routed and their precise delays are extracted from their shapes. Then, the locations of circuit blocks in the chip top level are optimized by performing timing analysis. 2) To synthesize the blocks, timing budgets are assigned according to the precise wire delays. 3) The block synthesis with the inter-block wire delays and re-assignment of the timing budgets for neighboring blocks are repeated until the timing budgets become feasible and consistent for the whole chip. 4) The entire chip layout, which involves placement and routing inside the blocks and detailed routing in the chip top level, is completed. As a result, no timing violation appears in the final timing analysis.