Systematic Methods for Design of VLSI Signal Processing Arrays for Communications Applications.

Abstract : This is the final report on our work under ONR Contract N00D14-86-K-0726, August 1, 1986 through July 31, 1989. The major results are, in two areas: (1) Studies of systematic design procedures for a class of structured algorithms often encountered in signal processing applications. These are what we have called Regular Iterative Algorithms (RIAs) for which our results are summarized in Section 2. ( 2) The other major area of effort was the study of a notable family of algorithms that are not in the RIA form, viz., those associated with Viterbi decoding of convolutional and trellis codes or more generally with shortest-path problems in graphs. (MM)

[1]  Thomas Kailath,et al.  Derivation, extensions and parallel implementation of regular iterative algorithms , 1989 .

[2]  Jr. G. Forney,et al.  The viterbi algorithm , 1973 .

[3]  P. G. Gulak,et al.  Decoding of Rate k/n Convolutional Codes in VLSI , 1988 .

[4]  Thomas Kailath VLSI ARRAY PROCESSORS FOR COMMUNICATIONS , CONTROL AND SIGNAL PROCESSING , 1987 .

[5]  Dan I. Moldovan,et al.  Data broadcasting in linearly scheduled array processors , 1984, ISCA 1984.

[6]  Yoichi Muraoka,et al.  Parallelism exposure and exploitation in programs , 1971 .

[7]  Richard M. Karp,et al.  The Organization of Computations for Uniform Recurrence Equations , 1967, JACM.

[8]  Thomas Kailath,et al.  Regular processor arrays for matrix algorithms with pivoting , 1988, [1988] Proceedings. International Conference on Systolic Arrays.

[9]  C. Rader Memory Management in a Viterbi Decoder , 1981, IEEE Trans. Commun..

[10]  C. Thomborson,et al.  A Complexity Theory for VLSI , 1980 .

[11]  T. Kailath,et al.  Some new algorithms for reconfiguring VLSI/WSI arrays , 1990, 1990 Proceedings. International Conference on Wafer Scale Integration.

[12]  Charles E. Leiserson,et al.  Optimizing Synchronous Circuitry by Retiming (Preliminary Version) , 1983 .

[13]  P. Glenn Gulak,et al.  VLSI Structures for Viterbi Receivers: Part I-General Theory and Applications , 1986, IEEE J. Sel. Areas Commun..

[14]  Thomas Kailath,et al.  Subspace scheduling and parallel implementation of non-systolic regular iterative algorithms , 1989, J. VLSI Signal Process..

[15]  Harold S. Stone,et al.  Parallel Processing with the Perfect Shuffle , 1971, IEEE Transactions on Computers.

[16]  J. Omura,et al.  On the Viterbi decoding algorithm , 1969, IEEE Trans. Inf. Theory.

[17]  Thomas Kailath,et al.  Regular iterative algorithms and their implementation on processor arrays , 1988, Proc. IEEE.

[18]  Jeffrey D Ullma Computational Aspects of VLSI , 1984 .

[19]  Franco P. Preparata,et al.  The cube-connected-cycles: A versatile network for parallel computation , 1979, 20th Annual Symposium on Foundations of Computer Science (sfcs 1979).

[20]  D.I. Moldovan,et al.  On the design of algorithms for VLSI systolic arrays , 1983, Proceedings of the IEEE.

[21]  G. David Forney,et al.  Structural analysis of convolutional codes via dual codes , 1973, IEEE Trans. Inf. Theory.

[22]  Sailesh K. Rao,et al.  What is a Systolic Algorithm? , 1986, Photonics West - Lasers and Applications in Science and Engineering.

[23]  Jehoshua Bruck,et al.  Efficient Algorithms for Reconfiguration in VLSI/WSI Arrays , 1990, IEEE Trans. Computers.

[24]  G. David Forney,et al.  Convolutional codes I: Algebraic structure , 1970, IEEE Trans. Inf. Theory.

[25]  Andrew J. Viterbi,et al.  Error bounds for convolutional codes and an asymptotically optimum decoding algorithm , 1967, IEEE Trans. Inf. Theory.

[26]  Gary L. Miller,et al.  New layouts for the shuffle-exchange graph(Extended Abstract) , 1981, STOC '81.

[27]  Thomas Kailath,et al.  Scheduling Linearly Indexed Assignment Codes , 1989, Photonics West - Lasers and Applications in Science and Engineering.

[28]  S. Kung,et al.  VLSI Array processors , 1985, IEEE ASSP Magazine.

[29]  Kung Yao,et al.  Systolic array processing of the Viterbi algorithm , 1989, IEEE Trans. Inf. Theory.

[30]  F. Leighton LAYOUT FOR THE SHUFFLE-EXCHANGE GRAPH AND LOWER BOUND TECHNIQUES FOR VLSI , 1982 .

[31]  Andrew J. Viterbi,et al.  Principles of Digital Communication and Coding , 1979 .