Design and Power Dissipation Consideration of PFAL CMOS v/s Conventional CMOS based 2:1 Multiplexer and Full Adder

With the integration of circuits, number of gates and transistors are increasing per chip area. However with integration in every digital circuit, the energy due to switching of gate doesn’t decrease at same rate as gates are increased per chip area. Due to this, power dissipation becomes significant and also reduction of heat becomes more complicated and expensive. The CMOS (complementary metal oxide semiconductor) Logic family is preferred for digital circuits due to its performance and impeccable noise margins over other families. However, in CMOS based circuits dynamic power requirement is becoming major concern in digital circuits. The aim ofthis paper is to carry out work that is focused on reducing the power dissipation in circuits, which increases with down scaling of circuits. The experimental work is carried out on 2:1 multiplexer and full adder circuit. Adiabatic logic with positive feedback (PFAL) is applied to redesign the circuit with input power taken as sinusoidal source of 3.3 V and analysis is done for power dissipation between conventional based CMOS circuit and PFAL based CMOS circuit. In comparison with the conventional CMOS based 2:1 multiplexer circuit, the designed PFAL based CMOS 2:1 multiplexer circuit has lesser power dissipation which is measured as 80.871 picoWatts as compared to conventional CMOS circuit which has 6.9090 nanoWatts with the same behavior of circuit. Also for full adder conventional CMOS circuit has 48.0452 picoWatts while PFAL based full adder has 3.9089 picoWatts.

[1]  Hemant Kumar,et al.  Adiabatic Design Implementation of Digital Circuits for Low Power Applications , 2020 .

[2]  Stefan Schmickl,et al.  An RF-Energy Harvester and IR-UWB Transmitter for Ultra-Low-Power Battery-Less Biosensors , 2020, IEEE Transactions on Circuits and Systems I: Regular Papers.

[3]  Izzet Kale,et al.  Investigating the effectiveness of Without Charge-Sharing Quasi-Adiabatic Logic for energy efficient and secure cryptographic implementations , 2018, Microelectron. J..

[4]  H. Fanet,et al.  MEMS four-terminal variable capacitor for low power capacitive adiabatic logic with high logic state differentiation , 2019, Nano Energy.

[5]  Roberto Saletti,et al.  Ultralow-power adiabatic circuit semi-custom design , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[6]  John S. Denker,et al.  2nd order adiabatic computation with 2N-2P and 2N-2N2P logic circuits , 1995, ISLPED '95.

[7]  Manfred Glesner,et al.  A low power sinusoidal clock , 2001, ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196).

[8]  J. S. Denker,et al.  A review of adiabatic computing , 1994, Proceedings of 1994 IEEE Symposium on Low Power Electronics.

[9]  Anantha P. Chandrakasan,et al.  Low-power CMOS digital design , 1992 .

[10]  Hendrikus J. M. Veendrick,et al.  Short-circuit dissipation of static CMOS circuitry and its impact on the design of buffer circuits , 1984 .

[11]  Massoud Pedram,et al.  Low power design methodologies , 1996 .

[12]  Salar Chamanian,et al.  An Adaptable Interface Circuit With Multistage Energy Extraction for Low-Power Piezoelectric Energy Harvesting MEMS , 2019, IEEE Transactions on Power Electronics.