论文信息 - Positive bias temperature instabilities on sub-nanometer EOT FinFETs

Positive bias temperature instabilities on sub-nanometer EOT FinFETs

PBTI degradation on FinFETs with HfO2/TiN gate stack (EOT < 1 nm) is studied. Thinner TiN layer decreases interfacial oxide thickness, and reduces PBTI lifetime. This behavior is consistent with the results in planar devices. Corner rounding effect on PBTI is also analyzed. Finally, charge pumping measurements on devices with several fin widths devices apparently show a higher density of defects in the top-wall high-j oxide than in the sidewall of the fin. This could explain more severe PBTI degradation. 2011 Elsevier Ltd. All rights reserved.

Guido Groeseneken | Moonju Cho | E. San Andrés | P. C. Feijoo | M. Togo

[1] J. Kavalieros,et al. High performance fully-depleted tri-gate CMOS transistors , 2003, IEEE Electron Device Letters.

[2] A. Hikavyy,et al. Highly manufacturable FinFETs with sub-10nm fin width and high aspect ratio fabricated with immersion lithography , 2007, 2007 IEEE Symposium on VLSI Technology.

[3] Moonju Cho,et al. Positive and negative bias temperature instability on sub-nanometer eot high-K MOSFETs , 2010, 2010 IEEE International Reliability Physics Symposium.

[4] B. Parvais,et al. Ultra low-EOT (5 Å) gate-first and gate-last high performance CMOS achieved by gate-electrode optimization , 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

[5] Jean-Pierre Colinge,et al. Multiple-gate SOI MOSFETs: device design guidelines , 2002 .

[6] Tsu-Jae King,et al. Improvement of FinFET electrical characteristics by hydrogen annealing , 2004, IEEE Electron Device Letters.

[7] J. Colinge. Silicon-on-Insulator Technology: Materials to VLSI , 1991 .

[8] B. Kaczer,et al. Reliability issues in MuGFET nanodevices , 2008, 2008 IEEE International Reliability Physics Symposium.

[9] Jean-Pierre Colinge,et al. Multiple-gate SOI MOSFETs , 2004 .