Exploring the evolution of NoC-based Spiking Neural Networks on FPGAs

Bio-inspired paradigms such as Spiking Neural Networks (SNNs) offer the potential to emulate the repairing and adaptive ability of the brain. This paper presents EMBRACE-FPGA, a scalable, configurable Network on Chip (NoC)-based SNN architecture, implemented on Xilinx Virtex II-Pro FPGA hardware. In association with a Genetic Algorithm-based hardware evolution platform, EMBRACE-FPGA provides a computing platform for intrinsic hardware evolution, which can be used to explore the evolution and adaptive capabilities of hardware SNNs. Results demonstrate the application of the hardware SNN evolution platform to solve the XOR benchmark problem.

[1]  Camel Tanougast,et al.  CuNoC: A Scalable Dynamic NoC for Dynamically Reconfigurable FPGAs , 2007, 2007 International Conference on Field Programmable Logic and Applications.

[2]  Luis A. Plana,et al.  SpiNNaker: Mapping neural networks onto a massively-parallel chip multiprocessor , 2008, 2008 IEEE International Joint Conference on Neural Networks (IEEE World Congress on Computational Intelligence).

[3]  John H. Holland,et al.  Adaptation in Natural and Artificial Systems: An Introductory Analysis with Applications to Biology, Control, and Artificial Intelligence , 1992 .

[4]  Wulfram Gerstner,et al.  Spiking Neuron Models , 2002 .

[5]  Simon Haykin,et al.  Neural Networks: A Comprehensive Foundation , 1998 .

[6]  Hieu Tat Nguyen,et al.  A gradient descent rule for spiking neurons emitting multiple spikes , 2005, Inf. Process. Lett..

[7]  Stephen Grossberg,et al.  Introduction: Spiking Neurons in Neuroscience and Technology , 2001, Neural Networks.

[8]  Wayne Luk,et al.  FPGA Accelerated Simulation of Biologically Plausible Spiking Neural Networks , 2009, 2009 17th IEEE Symposium on Field Programmable Custom Computing Machines.

[9]  Johannes Schemmel,et al.  Wafer-scale integration of analog neural networks , 2008, 2008 IEEE International Joint Conference on Neural Networks (IEEE World Congress on Computational Intelligence).

[10]  Fearghal Morgan,et al.  Investigating the Suitability of FPAAs for Evolved Hardware Spiking Neural Networks , 2008, ICES.

[11]  Wofgang Maas,et al.  Networks of spiking neurons: the third generation of neural network models , 1997 .

[12]  Jim Harkin,et al.  Novel Interconnect Strategy for Large Scale Implementations of Neural Networks , 2007 .

[13]  H. Markram The Blue Brain Project , 2006, Nature Reviews Neuroscience.

[14]  Raphael Rubin,et al.  Design of FPGA interconnect for multilevel metallization , 2004, IEEE Trans. Very Large Scale Integr. Syst..

[15]  Andres Upegui,et al.  An FPGA platform for on-line topology exploration of spiking neural networks , 2005, Microprocess. Microsystems.

[16]  Piotr Dudek,et al.  Reconfigurable platforms and the challenges for large-scale implementations of spiking neural networks , 2008, 2008 International Conference on Field Programmable Logic and Applications.

[17]  Liam McDaid,et al.  A programmable facilitating synapse device , 2008, 2008 IEEE International Joint Conference on Neural Networks (IEEE World Congress on Computational Intelligence).

[18]  Scott E. Fahlman,et al.  An empirical study of learning speed in back-propagation networks , 1988 .

[19]  Luca Benini,et al.  Networks on Chips : A New SoC Paradigm , 2022 .

[20]  Fearghal Morgan,et al.  Reconfigurable analogue hardware evolution of adaptive spiking neural network controllers , 2008, GECCO '08.

[21]  Fearghal Morgan,et al.  Intrinsic Hardware Evolution of Neural Networks in Reconfigurable Analogue and Digital Devices , 2006, 2006 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines.

[22]  Wolfgang Maass,et al.  Computation with spiking neurons , 2003 .

[23]  Gert Cauwenberghs,et al.  Dynamically Reconfigurable Silicon Array of Spiking Neurons With Conductance-Based Synapses , 2007, IEEE Transactions on Neural Networks.

[24]  K. Goossens,et al.  rdwired Networks on Chip in FPGAs to Unify Functional and Configuration Interconnects , 2008, Second ACM/IEEE International Symposium on Networks-on-Chip (nocs 2008).

[25]  Ammar Belatreche,et al.  Challenges for large-scale implementations of spiking neural networks on FPGAs , 2007, Neurocomputing.

[26]  J. Schemmel,et al.  Wafer-scale VLSI implementations of pulse coupled neural networks , 2007 .

[27]  Liam McDaid,et al.  A Reconfigurable and Biologically Inspired Paradigm for Computation Using Network-On-Chip and Spiking Neural Networks , 2009, Int. J. Reconfigurable Comput..

[28]  M.S. Kamel,et al.  Modular neural networks for solving high complexity problems , 2000, ICM 2000. Proceedings of the 12th International Conference on Microelectronics. (IEEE Cat. No.00EX453).

[29]  Lutz Prechelt,et al.  PROBEN 1 - a set of benchmarks and benchmarking rules for neural network training algorithms , 1994 .

[30]  Eduardo Ros,et al.  Real-time computing platform for spiking neurons (RT-spike) , 2006, IEEE Trans. Neural Networks.

[31]  Fearghal Morgan,et al.  Reconfigurable Hardware Evolution Platform for a Spiking Neural Network Robotics Controller , 2007, ARC.