Analysis of Nonideal Behaviors Based on INL/DNL Plots for SAR ADCs

This paper presents a comprehensive investigation of several important error sources for the successive-approximation register (SAR) analog-to-digital converters (ADCs). The error sources that we discuss in this paper include the dynamic comparator offset, the dynamic gain error of digital-to-analog converter (DAC), the capacitor mismatch of capacitive DAC, the incomplete settling of DAC, the undershoot of reference voltage, and the input signal coupling. The integral/differential nonlinearities (INL/DNL) of SAR ADCs that are resulted from these error sources are analyzed and addressed. A diagnostic procedure is presented to identify the possible error sources based on the INL/DNL plots. In addition, design suggestions for overcoming these problems are also offered and recommended in this paper.

[1]  Soon-Jyh Chang,et al.  A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure , 2010, IEEE Journal of Solid-State Circuits.

[2]  Yung-Hui Chung,et al.  A 12-bit 8.47-fJ/conversion-step 1-MS/s SAR ADC using capacitor-swapping technique , 2012, 2012 IEEE Asian Solid State Circuits Conference (A-SSCC).

[3]  Kiat Seng Yeo,et al.  An 8-bit 200-MSample/s Pipelined ADC With Mixed-Mode Front-End S/H Circuit , 2008, IEEE Transactions on Circuits and Systems I: Regular Papers.

[4]  Florence Azaïs,et al.  A Low-Cost BIST Architecture for Linear Histogram Testing of ADCs , 2001, J. Electron. Test..

[5]  Jai-Ming Lin,et al.  Mismatch-Aware Common-Centroid Placement for Arbitrary-Ratio Capacitor Arrays Considering Dummy Capacitors , 2012, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[6]  Franco Maloberti,et al.  A 10-bit 100-MS/s Reference-Free SAR ADC in 90 nm CMOS , 2010, IEEE Journal of Solid-State Circuits.

[7]  N. P. van der Meijs,et al.  A 26 $\mu$ W 8 bit 10 MS/s Asynchronous SAR ADC for Low Energy Radios , 2011, IEEE Journal of Solid-State Circuits.

[8]  Degang Chen,et al.  Code-Density Test of Analog-to-Digital Converters Using Single Low-Linearity Stimulus Signal , 2007, IEEE Transactions on Instrumentation and Measurement.

[9]  Yong-Bin Kim,et al.  A CMOS low-power low-offset and high-speed fully dynamic latched comparator , 2010, 23rd IEEE International SOC Conference.

[10]  Jiun-Lang Huang,et al.  An MCT-Based Bit-Weight Extraction Technique for Embedded SAR ADC Testing and Calibration , 2012, J. Electron. Test..

[11]  Chun-Yu Lin,et al.  Parasitic-aware sizing and detailed routing for binary-weighted capacitors in charge-scaling DAC , 2014, 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC).

[12]  Denis C. Daly,et al.  A 6-bit, 0.2 V to 0.9 V Highly Digital Flash ADC With Comparator Redundancy , 2009, IEEE Journal of Solid-State Circuits.

[13]  Degang Chen,et al.  Accurate testing of analog-to-digital converters using low linearity signals with stimulus error identification and removal , 2005, IEEE Transactions on Instrumentation and Measurement.

[14]  Chorng-Kuang Wang,et al.  A 10-bit 500-KS/s low power SAR ADC with splitting comparator for bio-medical applications , 2009, 2009 IEEE Asian Solid-State Circuits Conference.

[15]  Soon-Jyh Chang,et al.  10-bit 30-MS/s SAR ADC Using a Switchback Switching Method , 2013, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[16]  Daehwa Paik,et al.  A low-noise self-calibrating dynamic comparator for high-speed ADCs , 2008, 2008 IEEE Asian Solid-State Circuits Conference.

[17]  Yibo Wang,et al.  Symmetry constraint based on mismatch analysis for analog layout in SOI technology , 2008, 2008 Asia and South Pacific Design Automation Conference.

[18]  J. L. Dunkley,et al.  Systematic capacitance matching errors and corrective layout procedures , 1994 .

[19]  Soon-Jyh Chang,et al.  A 1-µW 10-bit 200-kS/s SAR ADC With a Bypass Window for Biomedical Applications , 2012, IEEE Journal of Solid-State Circuits.

[20]  Chung-Ming Huang,et al.  A 10b 100MS/s 1.13mW SAR ADC with binary-scaled error compensation , 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

[21]  Hsin-Wen Ting,et al.  A Histogram-Based Testing Method for Estimating A/D Converter Performance , 2008, IEEE Transactions on Instrumentation and Measurement.

[22]  Abhijit Chatterjee,et al.  Linearity Testing of A/D Converters Using Selective Code Measurement , 2008, J. Electron. Test..

[23]  J. Doernberg,et al.  Full-speed testing of A/D converters , 1984 .

[24]  Nobukazu Takai,et al.  SAR ADC algorithm with redundancy , 2008, APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems.

[25]  Yong-Bin Kim,et al.  Offset voltage analysis of dynamic latched comparator , 2011, 2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS).