Relationship between localized wafer shape changes induced by residual stress and overlay errors
暂无分享,去创建一个
[1] Allen H. Gabor,et al. The GridMapper challenge: how to integrate into manufacturing for reduced overlay error , 2010, Advanced Lithography.
[2] D. Perloff,et al. Automated electrical measurements of registration errors in step-and-repeat optical lithography systems , 1980, IEEE Transactions on Electron Devices.
[3] J. Buller,et al. Manufacturing issues related to RTP induced overlay errors in a global alignment stepper technology , 1996 .
[4] Milton Ohring,et al. Chapter 1 – A Review of Materials Science , 1992 .
[5] Harry J. Levinson,et al. Principles of Lithography , 2001 .
[6] Joseph P. Kirk,et al. Analysis Of Overlay Distortion Patterns , 1988, Advanced Lithography.
[7] Scott Halle,et al. Towards manufacturing of advanced logic devices by double-patterning , 2011, Advanced Lithography.
[8] Shouhong Tang,et al. Interferometry for wafer dimensional metrology , 2007, SPIE Optical Engineering + Applications.
[9] K. Bathe. Finite Element Procedures , 1995 .
[10] D.S. Perloff. A four-point electrical measurement technique for characterizing mask superposition errors on semiconductor wafers , 1978, IEEE Journal of Solid-State Circuits.
[11] Yuuki Ishii,et al. Improving scanner productivity and control through innovative connectivity application , 2006, SPIE Advanced Lithography.
[12] L. Freund,et al. Thin Film Materials: Stress, Defect Formation and Surface Evolution , 2004 .
[13] Sathish Veeraraghavan,et al. Predicting distortions and overlay errors due to wafer deformation during chucking on lithography scanners , 2009 .