Multi-Level Control of Resistive RAM (RRAM) Using a Write Termination to Achieve 4 Bits/Cell in High Resistance State

RRAM density enhancement is essential not only to gain market share in the highly competitive emerging memory sector but also to enable future high-capacity and power-efficient brain-inspired systems, beyond the capabilities of today’s hardware. In this paper, a novel design scheme is proposed to realize reliable and uniform multi-level cell (MLC) RRAM operation without the need of any read verification. RRAM quad-level cell (QLC) capability with 4 bits/cell is demonstrated for the first time. QLC is implemented based on a strict control of the cell programming current of 1T-1R HfO2-based RRAM cells. From a design standpoint, a self-adaptive write termination circuit is proposed to control the RESET operation and provide an accurate tuning of the analog resistance value of each cell of a memory array. The different resistance levels are obtained by varying the compliance current in the RESET direction. Impact of variability on resistance margins is simulated and analyzed quantitatively at the circuit level to guarantee the robustness of the proposed MLC scheme. The minimal resistance margin reported between two consecutive states is 2.1 kΩ along with an average energy consumption and latency of 25 pJ/cell and 1.65 μs, respectively.

[1]  Dietmar Fey,et al.  A Time-based Sensing Scheme for Multi-level Cell (MLC) Resistive RAM , 2019, 2019 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC).

[2]  Jiale Liang,et al.  Cross-Point Memory Array Without Cell Selectors—Device Characteristics and Data Storage Pattern Dependencies , 2010, IEEE Transactions on Electron Devices.

[3]  Y. Joly,et al.  Gate Voltage Matching Investigation for Low-Power Analog Applications , 2013, IEEE Transactions on Electron Devices.

[4]  Said Hamdioui,et al.  An Energy-Efficient Current-Controlled Write and Read Scheme for Resistive RAMs (RRAMs) , 2020, IEEE Access.

[5]  Daniele Ielmini,et al.  Resistive switching memories based on metal oxides: mechanisms, reliability and scaling , 2016 .

[6]  Pei-Kuei Tsung,et al.  Techology trend of edge AI , 2018, 2018 International Symposium on VLSI Design, Automation and Test (VLSI-DAT).

[7]  Seong-Ook Jung,et al.  Offset-Canceling Current-Sampling Sense Amplifier for Resistive Nonvolatile Memory in 65 nm CMOS , 2017, IEEE Journal of Solid-State Circuits.

[8]  Ajay Joshi,et al.  Design and Optimization of Nonvolatile Multibit 1 T 1 R Resistive RAM , 2014 .

[9]  Shimeng Yu,et al.  Emerging Memory Technologies: Recent Trends and Prospects , 2016, IEEE Solid-State Circuits Magazine.

[10]  K. Sakui,et al.  A CMOS bandgap reference circuit with sub-1-V operation , 1999 .

[11]  S. Menzel,et al.  3-Bit Multilevel Switching by Deep Reset Phenomenon in Pt/W/TaOX/Pt-ReRAM Devices , 2016, IEEE Electron Device Letters.

[12]  Ali Chehab,et al.  Oxide-based RRAM models for circuit designers: A comparative analysis , 2017, 2017 12th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS).

[13]  B. Chakrabarti,et al.  Multilevel Switching in Forming-Free Resistive Memory Devices With Atomic Layer Deposited ${\rm HfTiO}_{x}$ Nanolaminate , 2013, IEEE Electron Device Letters.

[14]  Norman P. Jouppi,et al.  Understanding the trade-offs in multi-level cell ReRAM memory design , 2013, 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC).

[15]  Fabien Clermidy,et al.  Design and Simulation of a 128 kb Embedded Nonvolatile Memory Based on a Hybrid RRAM (HfO2 )/28 nm FDSOI CMOS Technology , 2017, IEEE Transactions on Nanotechnology.

[16]  E. Vianello,et al.  Improvement of HfO2 based RRAM array performances by local Si implantation , 2017, 2017 IEEE International Electron Devices Meeting (IEDM).

[17]  Qi Liu,et al.  Investigation of resistive switching in Cu-doped HfO2 thin film for multilevel non-volatile memory applications , 2010, Nanotechnology.

[18]  J. Postel-Pellerin,et al.  ReRAM ON/OFF resistance ratio degradation due to line resistance combined with device variability in 28nm FDSOI technology , 2017, 2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS).

[19]  Meng-Fan Chang,et al.  Low ${\rm VDDmin}$ Swing-Sample-and-Couple Sense Amplifier and Energy-Efficient Self-Boost-Write-Termination Scheme for Embedded ReRAM Macros Against Resistance and Switch-Time Variations , 2015, IEEE Journal of Solid-State Circuits.

[20]  Tuo-Hung Hou,et al.  Improved multi-level control of RRAM using pulse-train programming , 2014, Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA).

[21]  Gang Chen,et al.  A 0.13 µm 8 Mb Logic-Based Cu $_{\rm x}$Si $_{\rm y}$O ReRAM With Self-Adaptive Operation for Yield Enhancement and Power Reduction , 2013, IEEE Journal of Solid-State Circuits.

[22]  H.-S. Philip Wong,et al.  Effect of Wordline/Bitline Scaling on the Performance, Energy Consumption, and Reliability of Cross-Point Memory Array , 2013, JETC.

[23]  Yunfei En,et al.  Layer‐dependent resistance variability assessment on 2048 8‐layer 3D vertical RRAMs , 2019, Electronics Letters.

[24]  U-In Chung,et al.  Multi-level switching of triple-layered TaOx RRAM with excellent reliability for storage class memory , 2012, 2012 Symposium on VLSI Technology (VLSIT).

[25]  Farooq Ahmad Khanday,et al.  Resistive Random Access Memory (RRAM): an Overview of Materials, Switching Mechanism, Performance, Multilevel Cell (mlc) Storage, Modeling, and Applications , 2020, Nanoscale Research Letters.

[26]  Wei Wang,et al.  Practical considerations of read-out circuits for passive, multi-level ReRAM arrays , 2016, 2016 IEEE International Conference on Manipulation, Manufacturing and Measurement on the Nanoscale (3M-NANO).

[27]  Meng-Fan Chang,et al.  A 16Mb dual-mode ReRAM macro with sub-14ns computing-in-memory and memory functions enabled by self-write termination scheme , 2017, 2017 IEEE International Electron Devices Meeting (IEDM).

[28]  Said Hamdioui,et al.  Density Enhancement of RRAMs using a RESET Write Termination for MLC Operation , 2021, 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[29]  Hassen Aziza,et al.  Impact of hump effect on MOSFET mismatch in the sub-threshold area for low power analog applications , 2010, 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology.

[30]  Ali Chehab,et al.  RRAM Device Models: A Comparative Analysis With Experimental Validation , 2019, IEEE Access.

[31]  G. Cibrario,et al.  Fundamental variability limits of filament-based RRAM , 2016, 2016 IEEE International Electron Devices Meeting (IEDM).

[32]  H. Aziza,et al.  A Capacitor-Less CMOS Neuron Circuit for Neuromemristive Networks , 2019, 2019 17th IEEE International New Circuits and Systems Conference (NEWCAS).

[33]  Ajay Joshi,et al.  Design and Optimization of Nonvolatile Multibit 1T1R Resistive RAM , 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[34]  Arnaud Virazel,et al.  Improving TID Radiation Robustness of a CMOS OxRAM-Based Neuron Circuit by Using Enclosed Layout Transistors , 2021, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[35]  Yiwei Liu,et al.  Observation of Conductance Quantization in Oxide‐Based Resistive Switching Memory , 2012, Advanced materials.

[36]  Alberto Bosio,et al.  Silicon Systems for Wireless LAN , 2020 .

[37]  H-S Philip Wong,et al.  Multi-level control of conductive nano-filament evolution in HfO2 ReRAM by pulse-train operations. , 2014, Nanoscale.

[38]  C. Muller,et al.  Evaluation of OxRAM cell variability impact on memory performances through electrical simulations , 2011, 2011 11th Annual Non-Volatile Memory Technology Symposium Proceeding.

[39]  Hassen Aziza,et al.  True Random Number Generator Integration in a Resistive RAM Memory Array Using Input Current Limitation , 2020, IEEE Transactions on Nanotechnology.

[40]  Fabien Clermidy,et al.  Compact Modeling Solutions for Oxide-Based Resistive Switching Memories (OxRAM) , 2014 .