ASIC implementation of a unified hardware architecture for non-key based cryptographic hash primitives

Hash algorithms are a class of cryptographic primitives used for fulfilling the requirements of integrity and authentication in cryptography. In this paper, we propose and present the ASIC implementation of 'HashChip', a hardware architecture aimed at providing a unified solution for three different commercial MDC (manipulation detection codes) hash primitives, namely MD5, SHA1 and RIPEMD160. The novelty of the work lies in the exploitation of the similarities in the structure of the three algorithms to obtain an optimized architecture. The performance analysis of a 0.18/spl mu/m ASIC implementation of the architecture has also been done.

[1]  Howard M. Heys,et al.  FPGA implementation of MD5 hash algorithm , 2001, Canadian Conference on Electrical and Computer Engineering 2001. Conference Proceedings (Cat. No.01TH8555).

[2]  Tung-Sang Ng,et al.  A unified architecture of MD5 and RIPEMD-160 hash algorithms , 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

[3]  Sandra Dominikus,et al.  A hardware implementation of MD4-family hash algorithms , 2002, 9th International Conference on Electronics, Circuits and Systems.

[4]  Jun Rim Choi,et al.  An efficient implementation of hash function processor for IPSEC , 2002, Proceedings. IEEE Asia-Pacific Conference on ASIC,.

[5]  Paul Douglas,et al.  Proceedings International Conference on Information Technology: Coding and Computing , 2002, Proceedings. International Conference on Information Technology: Coding and Computing.

[6]  Bart Preneel,et al.  RIPEMD-160: A Strengthened Version of RIPEMD , 1996, FSE.

[7]  William Stallings,et al.  Cryptography and Network Security: Principles and Practice , 1998 .

[8]  Alfred Menezes,et al.  Handbook of Applied Cryptography , 2018 .

[9]  Ronald L. Rivest,et al.  The MD5 Message-Digest Algorithm , 1992, RFC.

[10]  T. S. B. Sudarshan,et al.  Pre-silicon prototyping of a unified hardware architecture for cryptographic manipulation detection codes , 2004, Proceedings. 2004 IEEE International Conference on Field- Programmable Technology (IEEE Cat. No.04EX921).