Modeling and Characterization of High Frequency Effects in ULSI Interconnects

This paper discusses the accurate modeling of resistance R, inductance L and capacitance C in sub-100nm process node and their impacts on high frequency effects such as delay, crosstalk, and power/ground bounce. Models of interconnect (wire) resistances increase due to electron scattering at the surface and grain boundaries, and coupling capacitance of high aspect ratio interconnects for sub100nm process nodes are presented. It is observed from test chip measurement that the skin effect and inductive effects of Cu interconnect at high frequencies exhibit different behaviors compared to Al interconnect, presumably because of the presence of CMP dummy metal fills. It is shown that the incorporation of frequency dependent R and L is essential in the modeling and characterization of high frequency effects for high speed ULSI circuits.

[1]  Brian Young Digital Signal Integrity: Modeling and Simulation with Interconnects and Packages , 2000 .

[2]  S. Krishnan,et al.  An effective loop inductance model for general non-orthogonal interconnect with random capacitive coupling , 2002, Digest. International Electron Devices Meeting,.

[3]  Li Song,et al.  Atto-farad measurement and modeling of on-chip coupling capacitance , 2004, IEEE Electron Device Letters.

[4]  V. K. Tripathi,et al.  Characterization and modeling of multiple line interconnections from time domain measurements , 1994 .

[5]  N.D. Arora,et al.  Interconnect characterization of X architecture diagonal lines for VLSI design , 2005, IEEE Transactions on Semiconductor Manufacturing.

[6]  G. Schindler,et al.  Scaling laws for the resistivity increase of sub-100 nm interconnects , 2003, International Conference on Simulation of Semiconductor Processes and Devices, 2003. SISPAD 2003..

[7]  Hiroo Masuda,et al.  Design and measurement of an inductance-oscillator for analyzing inductance impact on on-chip interconnect delay , 2003, Fourth International Symposium on Quality Electronic Design, 2003. Proceedings..

[8]  N.D. Arora Modeling and characterization of copper interconnects for SoC design , 2003, International Conference on Simulation of Semiconductor Processes and Devices, 2003. SISPAD 2003..

[9]  P. Kapur,et al.  Technology and reliability constrained future copper interconnects. I. Resistance modeling , 2002 .

[10]  Massoud Pedram,et al.  Ground bounce in digital VLSI circuits , 2003, IEEE Trans. Very Large Scale Integr. Syst..

[11]  Yehea I. Ismail,et al.  Efficient model order reduction including skin effect , 2003, DAC '03.

[12]  Robert W. Dutton,et al.  High-frequency characterization of on-chip digital interconnects , 2002 .

[13]  A. Fujimura,et al.  A diagonal-interconnect architecture and its application to RISC core design , 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).

[14]  W. R. Eisenstadt,et al.  S-parameter-based IC interconnect transmission line characterization , 1992 .

[15]  Li Song,et al.  Test chip for inductance characterization and modeling for sub-100nm X architecture and Manhattan chip design , 2005, Proceedings of the 2005 International Conference on Microelectronic Test Structures, 2005. ICMTS 2005..