A Gbit-scale DRAM stacked capacitor technology with ECR MOCVD SrTiO/sub 3/ and RIE patterned RuO/sub 2/TiN storage nodes
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T. Sakuma | K. Shibahara | S. Ohnishi | K. Nakajima | H. Watanabe | K. Tokashiki | S. Yamamichi | P. Lesaicherre | H. Yamaguchi | K. Takemura | M. Yoshida | K. Satoh | Y. Miyasaka | H. Ono