Hardware security: Threat models and metrics

The globalized semiconductor supply chain is vulnerable to hardware attacks including: Trojans, piracy of intellectual properties (IPs) and/or overbuilding of integrated circuits (ICs), reverse engineering, side-channels, and counterfeiting. In this paper, we explain the threat models, the state-of-the-art defenses, and the metrics used to evaluate the defenses. The threat models outlined in this paper enables one to understand the attacks. Defenses and metrics can help defenders to build stronger countermeasures and evaluate them against other protection techniques using the metrics.

[1]  Simha Sethumadhavan,et al.  Side-channel vulnerability factor: A metric for measuring information leakage , 2012, 2012 39th Annual International Symposium on Computer Architecture (ISCA).

[2]  Debdeep Mukhopadhyay,et al.  Scan Based Side Channel Attacks on Stream Ciphers and Their Counter-Measures , 2008, INDOCRYPT.

[3]  Pankaj Rohatgi.  Improved Techniques for Side-Channel Analysis , 2009, Cryptographic Engineering.

[4]  Joseph Zambreno,et al.  Preventing IC Piracy Using Reconfigurable Logic Barriers , 2010, IEEE Design & Test of Computers.

[5]  Jeyavijayan Rajendran,et al.  VLSI testing based security metric for IC camouflaging , 2013, 2013 IEEE International Test Conference (ITC).

[6]  David A. Wagner,et al.  Defeating UCI: Building Stealthy and Malicious Hardware , 2011, 2011 IEEE Symposium on Security and Privacy.

[7]  George S. Taylor,et al.  Balanced self-checking asynchronous logic for smart card applications , 2003, Microprocess. Microsystems.

[8]  Farinaz Koushanfar,et al.  Consistency-based characterization for IC Trojan detection , 2009, 2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers.

[9]  Pankaj Rohatgi,et al.  Introduction to differential power analysis , 2011, Journal of Cryptographic Engineering.

[10]  Swarup Bhunia,et al.  HARPOON: An Obfuscation-Based SoC Design Methodology for Hardware Protection , 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[11]  D. Das,et al.  Semiconductor Manufacturers' Efforts to Improve Trust in the Electronic Part Supply Chain , 2007, IEEE Transactions on Components and Packaging Technologies.

[12]  Milo M. K. Martin,et al.  Overcoming an Untrusted Computing Base: Detecting and Removing Malicious Hardware Automatically , 2010, 2010 IEEE Symposium on Security and Privacy.

[13]  Mark Mohammad Tehranipoor,et al.  Trustworthy Hardware: Identifying and Classifying Hardware Trojans , 2010, Computer.

[14]  Jarrod A. Roy,et al.  Ending Piracy of Integrated Circuits , 2010, Computer.

[15]  Siva Sai Yerubandi,et al.  Differential Power Analysis , 2002 .

[16]  Miodrag Potkonjak,et al.  Robust IP watermarking methodologies for physical design , 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).

[17]  Berk Sunar,et al.  Trojan Detection using IC Fingerprinting , 2007, 2007 IEEE Symposium on Security and Privacy (SP '07).

[18]  Farinaz Koushanfar,et al.  Active Hardware Metering for Intellectual Property Protection and Security , 2007, USENIX Security Symposium.

[19]  Moti Yung,et al.  Practical leakage-resilient pseudorandom generators , 2010, CCS '10.

[20]  Tim Collins,et al.  Secure contactless smartcard ASIC with DPA protection , 2000, Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044).

[21]  Farinaz Koushanfar,et al.  High-sensitivity hardware Trojan detection using multimodal characterization , 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[22]  Sharad Malik,et al.  Reverse engineering digital circuits using functional analysis , 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[23]  I. Verbauwhede,et al.  A dynamic and differential CMOS logic with signal independent power consumption to withstand differential power analysis on smart cards , 2002, Proceedings of the 28th European Solid-State Circuits Conference.

[24]  Jarrod A. Roy,et al.  EPIC: Ending Piracy of Integrated Circuits , 2008, 2008 Design, Automation and Test in Europe.

[25]  Farinaz Koushanfar,et al.  A Unified Framework for Multimodal Submodular Integrated Circuits Trojan Detection , 2011, IEEE Transactions on Information Forensics and Security.

[26]  Moti Yung,et al.  Leakage Resilient Cryptography in Practice , 2010, Towards Hardware-Intrinsic Security.

[27]  Miodrag Potkonjak,et al.  Intellectual Property Metering , 2001, Information Hiding.

[28]  Simha Sethumadhavan,et al.  Silencing Hardware Backdoors , 2011, 2011 IEEE Symposium on Security and Privacy.

[29]  Farinaz Koushanfar,et al.  A Survey of Hardware Trojan Taxonomy and Detection , 2010, IEEE Design & Test of Computers.

[30]  Jeyavijayan Rajendran,et al.  Logic encryption: A fault analysis perspective , 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[31]  Yiorgos Makris,et al.  Proof-Carrying Hardware Intellectual Property: A Pathway to Trusted Module Acquisition , 2012, IEEE Transactions on Information Forensics and Security.

[32]  Jean-Pierre Seifert,et al.  Simple photonic emission analysis of AES , 2013, Journal of Cryptographic Engineering.

[33]  Marc Joye,et al.  Basics of Side-Channel Analysis , 2009, Cryptographic Engineering.

[34]  Miodrag Potkonjak,et al.  Trusted Integrated Circuits: A Nondestructive Hidden Characteristics Extraction Approach , 2008, Information Hiding.

[35]  Neil Walkinshaw,et al.  Reverse-Engineering Software Behavior , 2013, Adv. Comput..

[36]  Miodrag Potkonjak,et al.  Watermarking techniques for intellectual property protection , 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).

[37]  Pankaj Rohatgi,et al.  Electromagnetic Attacks and Countermeasures , 2009, Cryptographic Engineering.

[38]  Vinod Vaikuntanathan,et al.  Signature Schemes with Bounded Leakage Resilience , 2009, ASIACRYPT.

[39]  M. Potkonjak,et al.  FPGA fingerprinting techniques for protecting intellectual property , 1998, Proceedings of the IEEE 1998 Custom Integrated Circuits Conference (Cat. No.98CH36143).

[40]  Mark Mohammad Tehranipoor,et al.  Power supply signal calibration techniques for improving detection resolution to hardware Trojans , 2008, 2008 IEEE/ACM International Conference on Computer-Aided Design.

[41]  Mark Mohammad Tehranipoor,et al.  Path-delay fingerprinting for identification of recovered ICs , 2012, 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT).

[42]  Jeyavijayan Rajendran,et al.  Security analysis of logic obfuscation , 2012, DAC Design Automation Conference 2012.

[43]  Sanjit A. Seshia,et al.  Reverse engineering circuits using behavioral pattern mining , 2012, 2012 IEEE International Symposium on Hardware-Oriented Security and Trust.

[44]  Miodrag Potkonjak,et al.  Behavioral synthesis techniques for intellectual property protection , 2005, TODE.

[45]  Srinivas Devadas,et al.  Security Based on Physical Unclonability and Disorder , 2012 .

[46]  Yiorgos Makris,et al.  Hardware Trojan detection using path delay fingerprint , 2008, 2008 IEEE International Workshop on Hardware-Oriented Security and Trust.

[47]  Jeyavijayan Rajendran,et al.  Security analysis of integrated circuit camouflaging , 2013, CCS.

[48]  Dick James,et al.  The state-of-the-art in semiconductor reverse engineering , 2011, 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC).

[49]  David Naccache,et al.  The Sorcerer's Apprentice Guide to Fault Attacks , 2006, Proceedings of the IEEE.

[50]  Miodrag Potkonjak,et al.  Effective iterative techniques for fingerprinting design IP , 1999, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[51]  François-Xavier Standaert,et al.  A Tutorial on Physical Security and Side-Channel Attacks , 2004, FOSAD.

[52]  Yiorgos Makris,et al.  Parametric counterfeit IC detection via Support Vector Machines , 2012, 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT).

[53]  Miodrag Potkonjak,et al.  Hardware Trojan horse detection using gate-level characterization , 2009, 2009 46th ACM/IEEE Design Automation Conference.

[54]  Daniel E. Holcomb,et al.  Power-Up SRAM State as an Identifying Fingerprint and Source of True Random Numbers , 2009, IEEE Transactions on Computers.

[55]  Miodrag Potkonjak,et al.  Can EDA combat the rise of electronic counterfeiting? , 2012, DAC Design Automation Conference 2012.