Reduction of loop delay for digital symbol timing recovery systems using asynchronous equalization

Timing recovery loops with low loop delay are desirable. This paper presents receiver architectures with asynchronous equalization to reduce the loop delay. We propose a new asynchronous delayed least-mean-square (AD-LMS) adaptation algorithm together with an interaction-free loop to eliminate interaction between timing and equalization loops. In addition, a timing recovery scheme to reduce the timing jitter is developed. The proposed architecture can apply to 10GBASE-T systems. Simulation results show that the conventional approach suffers from the loop-interaction and the proposed method can eliminate this issue. Moreover, our approach has high phase margin, low gain peaking, and low jitter properties.