Real-time merging

A merge element combines two, concurrent, handshake streams. For every request received from a client, a merge element may send a request to its parent, and for each acknowledgement received from its parent, the merge element may send an acknowledgement to a client. We show that that a merge-element can provide bounded time response if its parent also has bounded time response. We present two new implementations of a merge: one that uses an arbiter, and one that uses Schmitt triggers but no arbiters. Based on these designs, we explore a class of concurrent computations that can be performed in guaranteed bounded time, and we raise some new questions about what is possible in asynchronous design.

[1]  Charles E. Molnar,et al.  Anomalous Behavior of Synchronizer and Arbiter Circuits , 1973, IEEE Transactions on Computers.

[2]  Martín Abadi,et al.  An old-fashioned recipe for real time , 1994, TOPL.

[3]  Ian M. Mitchell,et al.  Proving Newtonian arbiters Correct, almost surely , 1996 .

[4]  Ivan E. Sutherland,et al.  The counterflow pipeline processor architecture , 1994, IEEE Design & Test of Computers.

[5]  Mark R. Greenstreet,et al.  Verifying a self-timed divider , 1998, Proceedings Fourth International Symposium on Advanced Research in Asynchronous Circuits and Systems.

[6]  Daniel W. Dobberpuhl,et al.  The design and analysis of VLSI circuits , 1985 .

[7]  Michael Mendler,et al.  Newtonian arbiters cannot be proven correct , 1993, Formal Methods Syst. Des..

[8]  Ivan E. Sutherland,et al.  Micropipelines , 1989, Commun. ACM.

[9]  Grzegorz Rozenberg,et al.  Real-Time: Theory in Practice , 1991, Lecture Notes in Computer Science.

[10]  Leonard R. Marino,et al.  General theory of metastable operation , 1981, IEEE Transactions on Computers.

[11]  Alain J. Martin Programming in VLSI: from communicating processes to delay-insensitive circuits , 1991 .

[12]  Mark B. Josephs,et al.  CMOS design of the tree arbiter element , 1996, IEEE Trans. Very Large Scale Integr. Syst..

[13]  Ivan E. Sutherland,et al.  Counter ow Pipeline Processor Architecture , 1994 .

[14]  Eby G. Friedman,et al.  System Timing , 2000, The VLSI Handbook.

[15]  Thomas J. Chaney,et al.  Q-Modules: Internally Clocked Delay-Insensitive Modules , 1988, IEEE Trans. Computers.