VLSI-SoC: System-on-Chip in the Nanoscale Era – Design, Verification and Reliability

In recent years, the concept of Internet-of-Things (IoT) has attracted significant interests. Required by the applications, the IoT power optimization has become the key concern, which relies on innovations from all levels of device, circuits, and architectures. Meanwhile, the energy efficiency of existing IoT implementations based on the CMOS technology is fundamentally limited by the device physics and also the circuits and systems built on it. This chapter focuses on a different dimension, exploring how emerging beyond-CMOS devices, such as tunnel field effect transistor (TFET) and negative capacitance FET (NCFET), and the circuits and architectures built upon them, could extend the low-power design space to enable IoT applications with beyond-CMOS features.

[1]  S. Parkin,et al.  Magnetic Domain-Wall Racetrack Memory , 2008, Science.

[2]  G. De Micheli,et al.  Polarity control in double-gate, gate-all-around vertically stacked silicon nanowire FETs , 2012, 2012 International Electron Devices Meeting.

[3]  Enrico Macii,et al.  Multi-function logic synthesis of silicon and beyond-silicon ultra-low power pass-gates circuits , 2016, 2016 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC).

[4]  Tsung-Yi Wu,et al.  Low-leakage and low-power implementation of high-speed 65nm logic gates , 2008, 2008 IEEE International Conference on Electron Devices and Solid-State Circuits.

[5]  M. Schulz The end of the road for silicon? , 1999, Nature.

[6]  Byung-Gook,et al.  Application of Dynamic Pass-Transistor Logic to an 8-Bit Multiplier , 2000 .

[7]  Vojin G. Oklobdzija,et al.  Pass-transistor adiabatic logic using single power-clock supply , 1997 .

[8]  P. Kim,et al.  Energy band-gap engineering of graphene nanoribbons. , 2007, Physical review letters.

[9]  Alexandre Valentian,et al.  Limits of CMOS Technology and Interest of NEMS Relays for Adiabatic Logic Applications , 2015, IEEE Transactions on Circuits and Systems I: Regular Papers.

[10]  Cong Wang,et al.  Power System Design and Task Scheduling for Photovoltaic Energy Harvesting Based Nonvolatile Sensor Nodes , 2015 .

[11]  Rolf Drechsler,et al.  Towards One-Pass Synthesis , 2002, Springer US.

[12]  Sachin S. Sapatnekar,et al.  BDD decomposition for delay oriented pass transistor logic synthesis , 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[13]  H. Ohno,et al.  Magnetic Tunnel Junctions for Spintronic Memories and Beyond , 2007, IEEE Transactions on Electron Devices.

[14]  Luca Benini,et al.  Decision Diagrams and Pass Transistor Logic Synthesis , 1997 .

[15]  Sheng Wang,et al.  CMOS-based carbon nanotube pass-transistor logic integrated circuits , 2012, Nature Communications.

[16]  Narayanan Vijaykrishnan,et al.  Comparative Area and Parasitics Analysis in FinFET and Heterojunction Vertical TFET Standard Cells , 2016, ACM J. Emerg. Technol. Comput. Syst..

[17]  Wolfgang Fichtner,et al.  Low-power logic styles: CMOS versus pass-transistor logic , 1997, IEEE J. Solid State Circuits.

[18]  Enrico Macii,et al.  Ultra Low-Power Computation via Graphene-Based Adiabatic Logic Gates , 2014, 2014 17th Euromicro Conference on Digital System Design.

[19]  Arkady B. Zaslavsky,et al.  Context Aware Computing for The Internet of Things: A Survey , 2013, IEEE Communications Surveys & Tutorials.

[20]  Cong Wang,et al.  Storage-Less and Converter-Less Photovoltaic Energy Harvesting With Maximum Power Point Tracking for Internet of Things , 2016, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[21]  Enrico Macii,et al.  One-pass logic synthesis for graphene-based Pass-XNOR logic circuits , 2015, 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC).

[22]  Makoto Suzuki,et al.  A 1.5-ns 32-b CMOS ALU in double pass-transistor logic , 1993 .

[23]  J. Suehle,et al.  0.5 V Supply Voltage Operation of In 0.65 Ga 0.35 As/GaAs 0.4 Sb 0.6 Tunnel FET , 2015 .

[24]  Enrico Macii,et al.  Pass-XNOR logic: A new logic style for P-N junction based graphene circuits , 2014, 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[25]  Enrico Macii,et al.  Quasi-Adiabatic Logic Arrays for Silicon and Beyond-Silicon Energy-Efficient ICs , 2016, IEEE Transactions on Circuits and Systems II: Express Briefs.

[26]  Massoud Pedram,et al.  Low power design methodologies , 1996 .

[27]  Narayanan Vijaykrishnan,et al.  Dynamic Power and Energy Management for Energy Harvesting Nonvolatile Processor Systems , 2017, ACM Trans. Embed. Comput. Syst..

[28]  Giovanni De Micheli,et al.  Biconditional Binary Decision Diagrams: A Novel Canonical Logic Representation Form , 2014, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

[29]  Fabio Somenzi,et al.  CUDD: CU Decision Diagram Package Release 2.2.0 , 1998 .

[30]  Phaedon Avouris,et al.  Controllable p-n junction formation in monolayer graphene using electrostatic substrate engineering. , 2010, Nano letters.

[31]  E. Nowak,et al.  High-performance CMOS variability in the 65-nm regime and beyond. IBM J Res And Dev , 2006 .

[32]  Narayanan Vijaykrishnan,et al.  An examination of the architecture and system-level tradeoffs of employing steep slope devices in 3D CMPs , 2014, 2014 ACM/IEEE 41st International Symposium on Computer Architecture (ISCA).

[33]  S. Thompson,et al.  Moore's law: the future of Si microelectronics , 2006 .

[34]  S. Datta,et al.  Demonstration of p-type In0.7Ga0.3As/GaAs0.35Sb0.65 and n-type GaAs0.4Sb0.6/In0.65Ga0.35As complimentary Heterojunction Vertical Tunnel FETs for ultra-low power logic , 2015, 2015 Symposium on VLSI Technology (VLSI Technology).

[35]  Enrico Macii,et al.  Ultra-low power circuits using graphene p-n junctions and adiabatic computing , 2015, Microprocess. Microsystems.

[36]  Yu Wang,et al.  Solar Power Prediction Assisted Intra-task Scheduling for Nonvolatile Sensor Nodes , 2016, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.