Architecture and Design of Multichannel Millimeter-Wave Wireless NoC

The network-on-chip (NoC) is an enabling methodology to integrate many embedded cores on a single die. The existing method of implementing a NoC with planar metal interconnects is deficient due to high latency and significant power consumption arising out of multi-hop links used in data exchanges. To address these problems, this paper introduces design methodology for a wireless NoC with multiple nonoverlapping channels. The authors present both the physical layer design and the overall interconnection architecture.

[1]  Partha Pratim Pande,et al.  Design of an Energy-Efficient CMOS-Compatible NoC Architecture with Millimeter-Wave Wireless Interconnects , 2013, IEEE Transactions on Computers.

[2]  Radu Marculescu,et al.  On-chip communication architecture exploration: A quantitative evaluation of point-to-point, bus, and network-on-chip approaches , 2007, TODE.

[3]  Jian Xu,et al.  Demystifying 3D ICs: the pros and cons of going vertical , 2005, IEEE Design & Test of Computers.

[4]  Somayeh Sardashti,et al.  The gem5 simulator , 2011, CARN.

[5]  Jung Ho Ahn,et al.  Corona: System Implications of Emerging Nanophotonic Technology , 2008, 2008 International Symposium on Computer Architecture.

[6]  Anoop Gupta,et al.  The SPLASH-2 programs: characterization and methodological considerations , 1995, ISCA.

[7]  Partha Pratim Pande,et al.  Complex network-enabled robust wireless network-on-chip architectures , 2013, JETC.

[8]  Jri Lee,et al.  A low-power fully integrated 60GHz transceiver system with OOK modulation and on-board antenna assembly , 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[9]  Jason Cong,et al.  CMP network-on-chip overlaid with multi-band RF-interconnect , 2008, 2008 IEEE 14th International Symposium on High Performance Computer Architecture.

[10]  Jri Lee,et al.  A Low-Power Low-Cost Fully-Integrated 60-GHz Transceiver System With OOK Modulation and On-Board Antenna Assembly , 2009, IEEE Journal of Solid-State Circuits.

[11]  Antonio Robles,et al.  A Survey and Evaluation of Topology-Agnostic Deterministic Routing Algorithms , 2012, IEEE Transactions on Parallel and Distributed Systems.