Parallel Prefix Network Generation : an Application of Functional Programming

Parallel prefix networks are used in priority encoders, and to compute carries in fast adders. A typical microprocessor contains many such networks, and often they are hotspots. Although parallel prefix (or scan) has been much studied, surprisingly many questions remain unanswered. As geometries shrink, it is not at all clear how to make low power prefix networks with the desired timing properties. Here, I develop a method of writing very highly parameterised parallel prefix network generators in which we specify the combinators used to build the networks and then search for a topology that matches the given delay constraints. This first case study indicates that, in this functional setting, combinators and search fit well together. The resulting prefix networks are both small and shallow, and likely to be useful in low power applications.