Aggressive test power reduction through test stimuli transformation

Excessive switching activity during shift cycles in scan-based cores imposes considerable test power challenges. To ensure rapid and reliable test of SOCs, we propose a scan chain modification methodology that transforms the stimuli to be inserted to the scan chain through logic gate insertion between scan cells, reducing scan chain transitions. We introduce a novel matrix band algebra to formulate the impact of scan chain modifications on test stimuli transformations. Based on this analysis, we develop algorithms for transforming a set of test vectors into power-optimal test stimuli through cost-effective scan chain modifications. Experimental results show that scan-in power reductions exceeding 90% for test vectors and 99.5% for test cubes can be attained by the proposed methodology.

[1]  Patrick Girard,et al.  A modified clock scheme for a low power BIST test pattern generator , 2001, Proceedings 19th IEEE VLSI Test Symposium. VTS 2001.

[2]  Ozgur Sinanoglu,et al.  Scan power reduction through test data transition frequency analysis , 2002, Proceedings. International Test Conference.

[3]  G. Stewart.  Introduction to matrix computations , 1973 .

[4]  Hans-Joachim Wunderlich,et al.  Minimized Power Consumption for Scan-Based BIST , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

[5]  Nur A. Touba,et al.  Inserting test points to control peak power during scan testing , 2002, 17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2002. DFT 2002. Proceedings..

[6]  Bashir M. Al-Hashimi,et al.  Minimisation of power dissipation during test application in full-scan sequential circuits using primary input freezing , 2000 .

[7]  Lee Whetsel,et al.  Adapting scan architectures for low power operation , 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

[8]  Irith Pomeranz,et al.  Techniques for minimizing power dissipation in scan and combinational circuits during test application , 1998, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[9]  Kuen-Jong Lee,et al.  An input control technique for power reduction in scan circuits during test application , 1999, Proceedings Eighth Asian Test Symposium (ATS'99).

[10]  Sarita Thakar,et al.  On the generation of test patterns for combinational circuits , 1993 .

[11]  Ozgur Sinanoglu,et al.  Test power reduction through minimization of scan chain transitions , 2002, Proceedings 20th IEEE VLSI Test Symposium (VTS 2002).

[12]  Nur A. Touba,et al.  Reducing power dissipation during test using scan chain disable , 2001, Proceedings 19th IEEE VLSI Test Symposium. VTS 2001.

[13]  Ozgur Sinanoglu,et al.  Reducing Average and Peak Test Power Through Scan Chain Modification , 2003, J. Electron. Test..