A Fast, Robust Network Flow-based Standard-Cell Legalization Method for Minimizing Maximum Movement

The standard-cell placement legalization problem has become critical due to increasing design rule complexity and design utilization at 16nm and lower technology nodes. An ideal legalization approach should preserve the quality of the input placement in terms of routability and timing, as well as effectively manage white space availability and have low runtime. In this work, we present a robust legalization algorithm for standard cell placement that minimizes maximum cell movements fast and effectively based on a novel network-flow approach. The idea is inspired by path augmentation but with important differences. In contrast to the classical path augmentation approaches, we resolve bin overflows by finding several candidate paths that guarantee realizable (legal) flow solutions. In addition, we show how the proposed algorithm can be seamlessly extended to handle relevant cell edge spacing design rules. Our experimental results on the ISPD 2014 benchmarks illustrate that our proposed method yields 2.5x and 3.3x less maximum and average cell movement, respectively, and the runtime is significantly (18x) lower compared to best-in-class academic legalizers.

[1]  David Z. Pan,et al.  Diffusion-based placement migration , 2005, Proceedings. 42nd Design Automation Conference, 2005..

[2]  Gi-Joon Nam,et al.  ISPD 2006 Placement Contest: Benchmark Suite and Results , 2006, ISPD '06.

[3]  D. Chinnery,et al.  ISPD 2015 Benchmarks with Fence Regions and Routing Blockages for Detailed-Routing-Driven Placement , 2015, ISPD.

[4]  Ravindra K. Ahuja,et al.  Network Flows: Theory, Algorithms, and Applications , 1993 .

[5]  Ismail Bustany,et al.  POLAR: A High Performance Mixed-Size Wirelengh-Driven Placer With Density Constraints , 2015, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[6]  Steven Skiena,et al.  The Algorithm Design Manual , 2020, Texts in Computer Science.

[7]  David T. Westwick,et al.  Eh?Placer , 2016, ACM Trans. Design Autom. Electr. Syst..

[8]  Ulf Schlichtmann,et al.  Abacus: fast legalization of standard cell circuits with minimal movement , 2008, ISPD '08.

[9]  Minsik Cho,et al.  History-based VLSI legalization using network flow , 2010, Design Automation Conference.

[10]  Chris C. N. Chu,et al.  FastPlace 3.0: A Fast Multilevel Quadratic Placement Algorithm with Placement Congestion Control , 2007, 2007 Asia and South Pacific Design Automation Conference.

[11]  Ulrich Brenner BonnPlace Legalization: Minimizing Movement by Iterative Augmentation , 2013, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[12]  Natarajan Viswanathan,et al.  ICCAD-2013 CAD contest in placement finishing and benchmark suite , 2013, 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[13]  Andrew A. Kennings,et al.  Detailed placement accounting for technology constraints , 2014, 2014 22nd International Conference on Very Large Scale Integration (VLSI-SoC).

[14]  Evangeline F. Y. Young,et al.  Cell density-driven detailed placement with displacement constraint , 2014, ISPD '14.

[15]  Andrew B. Kahng,et al.  On legalization of row-based placements , 2004, GLSVLSI '04.

[16]  Edsger W. Dijkstra,et al.  A note on two problems in connexion with graphs , 1959, Numerische Mathematik.

[17]  Ismail Bustany,et al.  ISPD 2014 benchmarks with sub-45nm technology rules for detailed-routing-driven placement , 2014, ISPD '14.