Compact modeling of nano-scale trapezoidal cross-sectional FinFETs

Analytical compact model for the drain current and trans-capacitances of undoped or lightly doped nanoscale FinFETs with trapezoidal cross section is presented. The compact model of rectangular FinFETs is applied in trapezoidal FinFETs using the concept of the equivalent device parameters. The model is compared with the results of three-dimensional numerical device simulations. The overall results reveal the very good accuracy of the proposed compact model, making it suitable for circuit design simulation tools.

[1]  G. Ghibaudo,et al.  Compact Capacitance Model of Undoped or Lightly Doped Ultra-Scaled Triple-Gate FinFETs , 2012, IEEE Transactions on Electron Devices.

[2]  G. Ghibaudo,et al.  Compact Model of Drain Current in Short-Channel Triple-Gate FinFETs , 2012, IEEE Transactions on Electron Devices.

[3]  Gerard Ghibaudo,et al.  Symmetrical unified compact model of short-channel double-gate MOSFETs , 2012 .

[4]  Christophe Lallement,et al.  Physics-based compact model for ultra-scaled FinFETs , 2011 .

[5]  F. Gamiz,et al.  Equivalent Oxide Thickness of Trigate SOI MOSFETs With High- $\kappa$ Insulators , 2009, IEEE Transactions on Electron Devices.

[6]  Yuan Taur,et al.  A Review on Compact Modeling of Multiple-Gate MOSFETs , 2009, IEEE Transactions on Circuits and Systems I: Regular Papers.

[7]  A. Kloes,et al.  Three-Dimensional Closed-Form Model for Potential Barrier in Undoped FinFETs Resulting in Analytical Equations for $V_{T}$ and Subthreshold Slope , 2008, IEEE Transactions on Electron Devices.

[8]  G. Ghibaudo,et al.  Semianalytical Modeling of Short-Channel Effects in Lightly Doped Silicon Trigate MOSFETs , 2008, IEEE Transactions on Electron Devices.

[9]  D. Flandre,et al.  A 3-D Analytical Physically Based Model for the Subthreshold Swing in Undoped Trigate FinFETs , 2007, IEEE Transactions on Electron Devices.

[10]  L. Mathew,et al.  Physical insights regarding design and performance of independent-gate FinFETs , 2005, IEEE Transactions on Electron Devices.

[11]  Jean-Pierre Colinge,et al.  Multiple-gate SOI MOSFETs: device design guidelines , 2002 .

[12]  Vivek De,et al.  Intrinsic MOSFET parameter fluctuations due to random dopant placement , 1997, IEEE Trans. Very Large Scale Integr. Syst..