X-Sources Analysis for Improving the Test Quality
暂无分享,去创建一个
[1] Kun-Han Tsai. Test coverage debugging for designs with timing exception paths , 2016, 2016 International Symposium on VLSI Design, Automation and Test (VLSI-DAT).
[2] Kun-Han Tsai,et al. Test Coverage Analysis for Designs with Timing Exceptions , 2017, 2017 IEEE 26th Asian Test Symposium (ATS).
[3] K.-T. Cheng,et al. A Partial Scan Method for Sequential Circuits with Feedback , 1990, IEEE Trans. Computers.
[4] J. Rajski,et al. Testing the hold time fault for large industrial design , 2008, 2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT).
[5] Dhiraj Goswami,et al. Test Generation in the Presence of Timing Exceptions and Constraints , 2007, 2007 44th ACM/IEEE Design Automation Conference.
[6] Kun-Han Tsai,et al. Design rule check on the clock gating logic for testability and beyond , 2013, 2013 IEEE International Test Conference (ITC).
[7] Kun-Han Tsai,et al. Enhanced testing of clock faults , 2007, 2007 IEEE International Test Conference.