Digitally Controlled 10-Gb/s Adjustable Delay Line for Adaptive Filter Design in standard CMOS Technology

In order for adaptive filter design to achieve optimum performance, the latency around the loop needs to be exactly designed for each targeted data rates. Due to unforeseen parasitic effects, latency has been major design issues for adaptive filters design with decision feedback topologies. In this paper, a digitally controlled adjustable delay line IC is presented that can be tuned with 3-ps resolution with a modular-based digital-to-analog converter (DAC) design. The proposed adjustable delay line achieved wide bandwidth for 10-Gb/sec data throughput while demonstrating bit-error rate (BER) improvement for the given equalizer design over various band-limited channels. The proposed IC is implemented in a 0.18-mum standard CMOS technology.

[1]  Gu-Yeon Wei,et al.  An adaptive PAM-4 5-Gb/s backplane transceiver in 0.25-/spl mu/m CMOS , 2003 .

[2]  V. Stojanovic,et al.  Equalization and clock recovery for a 2.5-10Gb/s 2-PAM/4-PAM backplane transceiver cell , 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..

[3]  M. Maeng,et al.  A 0.18/spl mu/m CMOS equalizer with an improved multiplier for 4-PAM/20Gbps throughput over 20 inch FR-4 backplane channels , 2004, 2004 IEEE MTT-S International Microwave Symposium Digest (IEEE Cat. No.04CH37535).