Buffer planning based on block exchanging

This paper studies the buffer planning problem for interconnect-driven floorplanning. With development of deep submicron technology, interconnect plays dominant role and buffer-insertion is a most flexible and efficient way to resolve this problem. However, buffer-planning on a fixed topology which only optimizes area or total wire-length is not reasonable and at the same time, trying to generate a topology which optimizes timing is much too time-consuming. We develop an algorithm which exchanges blocks of similar size to optimize timing constraint. With this algorithm applied, based on a topology which has already optimized area, we generate a packing that doesn't increase total area but exchanges block's position so that interconnect performance could be optimized in reasonable time