A Second-Order Purely VCO-Based CT Δ∑ ADC Using a Modified DPLL in 40-nm CMOS

This paper presents a power-efficient purely VCO-based 2nd-order CT Δ∑ ADC featuring a modified DPLL structure. It combines a VCO with an SRO-based TDC, which enables 2nd-order noise shaping without any OTA. The nonlinearity of the front-end VCO is mitigated by putting it inside a closed loop. A multi-PFD scheme reduces the VCO center frequency and power. The proposed architecture also realizes an intrinsic tri-level DWA. A prototype ADC in 40-nm CMOS process achieves a Schreier FoM of 170.3 dB with a DR of 72.7 dB over 5.2-MHz BW, while consuming 0.91 mW under 1.1-V supply.