Thermal-stress analysis of SOIC packages and interconnections

Thermal stresses in surface-mounted small-outline integrated-circuit (SOIC) assemblies are studied using the finite-element method. Emphasis is placed on the effects of solder-joint geometry on package and interconnection reliability. In addition, the problem of voids in solder joints is addressed. Seven different solder-joint geometries and six different void sizes are considered. It is found that the voids in the solder joint increase the stresses acting on it. The results presented can provide guidelines for solder joint inspection.<<ETX>>

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