Layout proximity effects and device extraction in circuit designs

The scaling of CMOS technology intensifies the interaction between design and process at 45nm or below, causing strong layout-dependent proximity effects. Photolithography, strain silicon engineering, and ion implantation are the primary causes of those effects, whose impacts to design can be mitigated via restrictive design rules and accurate modeling. A novel approach is proposed that seamlessly integrates physical models with geometry processing for device extraction, alleviating the overheads to LVS and circuit simulators in conventional design flow.