Moduli selection in RNS for efficient VLSI implementation

In this paper, we carry out a study on an important issue concerning the use of residue numbers in the design of digital systems, namely, the moduli selection. Based on a new formulation of the Chinese remainder theorem and the efficient residue-to-binary (R/B) converters designed therefrom, we propose a guideline for the selection of the low-cost moduli sets for different dynamic ranges. These sets consist of the low-cost moduli of the form 2/sup n/, ( 2/sup n/-1) or (2/sup n/ + 1), which can offer simplified modulo adders and multipliers. It is shown that for medium dynamic ranges (less than 22 bits), the three-moduli set {2/sup n/,2/sup n/ + 1,2/sup n/ - 1} is the most efficient one in terms of the design of a complete RNS system. On the other hand, for large dynamic ranges (equal to or larger than 22 bits), the general-moduli set in the form (2/sup n/, 2/sup n/ + 1,2/sup n/ - 1,2/sup n/ /spl plusmn/1,...,2/sup n/, /spl plusmn/1), with a length greater than three, is the most efficient one. These results provide the possibility of a wide range of applications of the residue number system in the design of DSP, telecommunication and cryptography systems.

[1]  Hong Shen,et al.  Adder based residue to binary number converters for (2n-1, 2n, 2n+1) , 2002, IEEE Trans. Signal Process..

[2]  W. Kenneth Jenkins,et al.  The use of residue number systems in the design of finite impulse response digital filters , 1977 .

[3]  Wei Wang,et al.  An area-time-efficient residue-to-binary converter , 2000, Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144).

[4]  Yutai Ma.  A Slimplified Architecture for Modulo (2n + 1) Multiplication , 1998, IEEE Trans. Computers.

[5]  Behrooz Parhami,et al.  Computer arithmetic - algorithms and hardware designs , 1999 .

[6]  Fred J. Taylor,et al.  RNS implementation of FIR filters based on distributed arithmetic using field-programmable logic , 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).

[7]  Yuke Wang,et al.  A study of the residue-to-binary converters for the three-moduli sets , 2003 .

[8]  A. Hiasat.  Efficient residue to binary converter , 2003 .

[9]  Ahmad A. Hiasat,et al.  High-Speed and Reduced-Area Modular Adder Structures for RNS , 2002, IEEE Trans. Computers.

[10]  Wei Wang,et al.  A note on "A high-speed residue-to-binary converter for three-moduli (2/sup k/ 2/sup k/ - 1, 2/sup k-1/ - 1) RNS and a scheme for its VLSI implementation" , 2000 .

[11]  Michael A. Soderstrand,et al.  Residue number system arithmetic: modern applications in digital signal processing , 1986 .