Noise-aware simulation-based sizing and optimization of clocked comparators

Comparators are essential components of ADCs, and largely affect their overall performance. Among the performance metrics of the comparator, the noise is the most difficult to estimate and simulate, specially for circuits that present a time-varying behavior such as clocked comparators. In this work we present a framework to size and optimize comparators which uses periodic steady-state (PSS) and periodic noise (PNOISE) analyses, commonly employed for RF circuits, together with an optimization kernel based on evolutionary algorithms. We present a case study comparator design, taking into account noise, power and delay. The results show that the proposed framework minimizes these parameters and achieves systematic convergence to consistent Pareto fronts in a short timespan (approximately 27 mins). Furthermore, the accuracy of the PSS/PNOISE noise estimation method is validated through comparison to extensive transient noise simulations, showing a difference standard deviation of 3.47 % between the two methods.