G-vector: A New Model for Glitch Analysis in Logic Circuits

One of the major factors which contribute to the power consumption in CMOS combinational logic circuits is the switching activities in the circuits. Many of such switching activities are due to spurious pulses, called glitches. In this paper, we propose a new model for describing signals that contain glitches, called G-vector. Unlike the previous works in which their primary concern is modeling the propagation of glitches to count the number of glitches in the circuits, our G-vector provides a general, but effective model for generation, propagation and elimination of glitches, enabling us to not only count the number of glitches but also locate the glitches so that such information can be utilized by system tools for the reduction of the number of glitches in the circuits. We provide a set of experimental results to demonstrate the effectiveness of our model.

[1]  Massoud Pedram,et al.  Power minimization in IC design: principles and applications , 1996, TODE.

[2]  Ping Yang,et al.  A Monte Carlo approach for power estimation , 1993, IEEE Trans. Very Large Scale Integr. Syst..

[3]  Kurt Keutzer,et al.  Estimation of average switching activity in combinational and sequential circuits , 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.

[4]  Melvin A. Breuer,et al.  Procedures for Eliminating Static and Dynamic Hazards in Test Generation , 1974, IEEE Transactions on Computers.

[5]  Melvin A. Breuer,et al.  Digital systems testing and testable design , 1990 .

[6]  Chi-Ying Tsui,et al.  Gate-level power estimation using tagged probabilistic simulation , 1998, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[7]  Luca Benini,et al.  Analysis of glitch power dissipation in CMOS ICs , 1995, ISLPED '95.

[8]  Radu Marculescu,et al.  Probabilistic modeling of dependencies during switching activity analysis , 1998, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[9]  Massoud Pedram,et al.  An approach for multilevel logic optimization targeting low power , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[10]  Daniel W. Lewis.  Hazard detection by a quinary simulation of logic devices with bounded propagation delays , 1972, DAC '72.

[11]  Ibrahim N. Hajj,et al.  Probabilistic simulation for reliability analysis of CMOS VLSI circuits , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[12]  John P. Hayes,et al.  Uncertainty, Energy, and Multiple-Valued Logics , 1986, IEEE Transactions on Computers.

[13]  Mary Jane Irwin,et al.  Accurate Estimation of Combinational Circuit Activity , 1995, 32nd Design Automation Conference.

[14]  Farid N. Najm,et al.  Transition density, a stochastic measure of activity in digital circuits , 1991, 28th ACM/IEEE Design Automation Conference.

[15]  Massoud Pedram,et al.  Stratified random sampling for power estimation , 1996, Proceedings of International Conference on Computer Aided Design.

[16]  D. Huffman.  A Method for the Construction of Minimum-Redundancy Codes , 1952 .

[17]  Robert K. Brayton,et al.  Decomposition of logic functions for minimum transition activity , 1995, Proceedings the European Design and Test Conference. ED&TC 1995.

[18]  Anantha P. Chandrakasan,et al.  Low Power Digital CMOS Design , 1995 .

[19]  Ping Yang,et al.  Pattern-independent current estimation for reliability analysis of CMOS circuits , 1988, 25th ACM/IEEE, Design Automation Conference.Proceedings 1988..