Design of a Low Voltage Class-AB CMOS Super Buffer Amplifier with Sub Threshold and Leakage Control

This paper describes a CMOS analogy voltage supper buffer designed to have extremely low static current Consumption as well as high current drive capability. A new technique is used to reduce the leakage power of class-AB CMOS buffer circuits without affecting dynamic power dissipation. The name of applied technique is TRANSISTOR GATING TECHNIQUE, which gives the high speed buffer with the reduced low power dissipation (1.105%), low leakage and reduced area (3.08%) also. The proposed buffer is simulated at 45nm CMOS technology and the circuit is operated at 3.3V supply[11]. Consumption is comparable to the switching component. Reports indicate that 40% or even higher percentage of the total power consumption is due to the leakage of transistors. This percentage will increase with technology scaling unless effective techniques are introduced to bring leakage under control. This article focuses on circuit optimization and Design automation techniques to accomplish this goal [9].

[1]  Stephanie Thalberg,et al.  Fundamentals Of Modern Vlsi Devices , 2016 .

[2]  Farzan Fallah,et al.  Runtime mechanisms for leakage current reduction in CMOS VLSI circuits , 2002, Proceedings of the International Symposium on Low Power Electronics and Design.

[3]  Ka Nang Leung,et al.  A CMOS Low-Dropout Regulator With a Momentarily Current-Boosting Voltage Buffer , 2010, IEEE Transactions on Circuits and Systems I: Regular Papers.

[4]  Massimo Alioto,et al.  Power-Aware Design of Nanometer MCML Tapered Buffers , 2008, IEEE Transactions on Circuits and Systems II: Express Briefs.

[5]  T. Fujita,et al.  A 0.9 V 150 MHz 10 mW 4 mm/sup 2/ 2-D discrete cosine transform core processor with variable-threshold-voltage scheme , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.

[6]  Salvatore Pennisi,et al.  A low-quiescent current two-input/output buffer amplifier for LCDs , 2012, 2012 IEEE International Symposium on Circuits and Systems.

[7]  Ibrahim N. Hajj,et al.  Maximum leakage power estimation for CMOS circuits , 1999, Proceedings IEEE Alessandro Volta Memorial Workshop on Low-Power Design.

[8]  C. Luchini,et al.  [High speed]. , 1969, Revista De La Escuela De Odontologia, Universidad Nacional De Tucuman, Facultad De Medicina.

[9]  Jeffrey Bokor,et al.  Dynamic threshold-voltage MOSFET (DTMOS) for ultra-low voltage VLSI , 1997 .

[10]  Chi-Chang Wang,et al.  A 3.3-V/5-V low power TTL-to-CMOS input buffer , 1998 .

[11]  藤田 哲也,et al.  A 0.9V 150MHz 10mW 4mm^2 2-D Discrete Cosine Transform Core Processor with Variable Threshold-Voltage (VT) Scheme , 1996 .

[12]  Sharma,et al.  Comparison among Different Cmos Inverter for Low Leakage at Different Technologies , 2010 .

[13]  T. Saether,et al.  High speed, high linearity CMOS buffer amplifier , 1996 .

[14]  Shin'ichiro Mutoh,et al.  1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS , 1995, IEEE J. Solid State Circuits.

[15]  Yuan Taur,et al.  Fundamentals of Modern VLSI Devices , 1998 .