Diagonal test and diagnostic schemes for flash memories

Embedded flash memory plays an increasingly important role for system-on-chip (SOC), especially for battery-powered devices. Testing and diagnosis of embedded flash memory is becoming one of the key development and production issues for many SOC products. Moreover, high density, high capacity, and the integration of heterogeneous cores in an SOC results in long test time, which in turn lead to high test cost. In this paper we propose a new diagonal test algorithm for flash memory that effectively reduces the test time without sacrificing the fault coverage. Both disturb faults and conventional RAM faults are covered. A diagnostic algorithm is also presented, which can distinguish among all the disturb faults and most of the conventional RAM faults. Finally, a built-in self-diagnosis (BISD) scheme is proposed. The BISD circuit implements our algorithms and user-defined ones, and its area overhead is low, e.g., it contains only about 2,551 gates (2-3%) for a 2 Mb flash memory. The test time by our diagonal test is reduced by about 42.69% as compared with the best March-like algorithm reported so far.

[1]  Jin-Fu Li,et al.  A built-in self-test and self-diagnosis scheme for embedded SRAM , 2000, Proceedings of the Ninth Asian Test Symposium.

[2]  Cheng-Wen Wu,et al.  Simulation-based test algorithm generation for random access memories , 2000, Proceedings 18th IEEE VLSI Test Symposium.

[3]  Jen-Chieh Yeh,et al.  Flash memory built-in self-test using March-like algorithms , 2002, Proceedings First IEEE International Workshop on Electronic Design, Test and Applications '2002.

[4]  Paolo Prinetto,et al.  Industrial BIST of embedded RAMs , 1995, IEEE Design & Test of Computers.

[5]  Gaetano Palumbo,et al.  Built in self test for low cost testing of a 60MHz synchronous flash memory , 2001, Proceedings Seventh International On-Line Testing Workshop.

[6]  Carla Golla,et al.  Flash Memories , 1999 .

[7]  Kewal K. Saluja,et al.  Testing reconfigured RAM's and scrambled address RAM's for pattern sensitive faults , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[8]  Kewal K. Saluja,et al.  Testing flash memories , 2000, VLSI Design 2000. Wireless and Digital Imaging in the Millennium. Proceedings of 13th International Conference on VLSI Design.

[9]  Zaid Al-Ars,et al.  Functional memory faults: a formal notation and a taxonomy , 2000, Proceedings 18th IEEE VLSI Test Symposium.

[10]  Piero Olivo,et al.  Self-learning signature analysis for non-volatile memory testing , 1996, Proceedings International Test Conference 1996. Test and Design Validity.

[11]  A. J. van de Goor,et al.  Testing Semiconductor Memories: Theory and Practice , 1998 .

[12]  Kewal K. Saluja,et al.  Flash memory disturbances: modeling and test , 2001, Proceedings 19th IEEE VLSI Test Symposium. VTS 2001.

[13]  Tetsuo Endoh,et al.  Reliability issues of flash memory cells , 1993, Proc. IEEE.

[14]  Jen-Chieh Yeh,et al.  RAMSES-FT: a fault simulator for flash memory testing and diagnostics , 2002, Proceedings 20th IEEE VLSI Test Symposium (VTS 2002).

[15]  Cheng-Wen Wu,et al.  Error catch and analysis for semiconductor memories using March tests , 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).

[16]  Cheng-Wen Wu,et al.  A Programmable BIST Core for Embedded DRAM , 1999, IEEE Des. Test Comput..

[17]  Bruce F. Cockburn Tutorial on semiconductor memory testing , 1994, J. Electron. Test..

[18]  Marian Marinescu,et al.  Simple and Efficient Algorithms for Functional RAM Testing , 1982, ITC.