A CNN-Specific Integrated Processor

Integrated Processors (IP) are algorithm-specific cores that either by programming or by configuration can be re-used within many microelectronic systems. This paper looks at Cellular Neural Networks (CNN) to become realized as IP. First current digital implementations are reviewed, and the memoryprocessor bandwidth issues are analyzed. Then a generic view is taken on the structure of the network, and a new intra-communication protocol based on rotating wheels is proposed. It is shown that this provides for guaranteed high-performance with a minimal network interface. The resulting node is small and supports multi-level CNN designs, giving the system a 30-fold increase in capacity compared to classical designs. As it facilitates multiple operations on a single image, and single operations on multiple images, with minimal access to the external image memory, balancing the internal and external data transfer requirements optimizes the system operation. In conventional digital CNN designs, the treatment of boundary nodes requires additional logic to handle the CNN value propagation scheme. In the new architecture, only a slight modification of the existing cells is necessary to model the boundary effect. A typical prototype for visual pattern recognition will house 4096 CNN cells with a 2% overhead for making it an IP.

[1]  Mark Harm ter Brugge Morphological design of Discrete-Time Cellular Neural Networks , 2005 .

[2]  William J. Dally,et al.  Imagine: Media Processing with Streams , 2001, IEEE Micro.

[3]  Ángel Rodríguez-Vázquez,et al.  ACE4k: An analog I/O 64×64 visual microprocessor chip with 7-bit analog accuracy , 2002, Int. J. Circuit Theory Appl..

[4]  Ángel Rodríguez-Vázquez,et al.  The Eye-RIS CMOS Vision System , 2008 .

[5]  Luca Benini,et al.  Networks on Chips : A New SoC Paradigm , 2022 .

[6]  Péter Szolgay,et al.  Configurable multi-layer CNN-UM emulator on FPGA , 2002, Proceedings of the 2002 7th IEEE International Workshop on Cellular Neural Networks and Their Applications.

[7]  José Manuel Ferrández,et al.  Discrete-Time Cellular Neural Networks in FPGA , 2007, 15th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2007).

[8]  Dake Liu,et al.  SoCBUS: switched network on chip for hard real time embedded systems , 2003, Proceedings International Parallel and Distributed Processing Symposium.

[9]  Lin-Bao Yang,et al.  Cellular neural networks: theory , 1988 .

[10]  Leon O. Chua,et al.  Cellular neural networks: applications , 1988 .

[11]  Kees Goossens,et al.  AEthereal network on chip: concepts, architectures, and implementations , 2005, IEEE Design & Test of Computers.

[12]  André DeHon,et al.  The Density Advantage of Configurable Computing , 2000, Computer.

[13]  Ralph K. Cavin,et al.  An Assessment of Integrated Digital Cellular Automata Architectures , 2008, Computer.

[14]  Lambert Spaanenburg,et al.  Hand veins feature extraction using DT-CNNS , 2007, SPIE Microtechnologies.

[15]  David A. Patterson,et al.  Computer Architecture: A Quantitative Approach , 1969 .

[16]  Ángel Rodríguez-Vázquez,et al.  ACE4k: An analog I/O 64×64 visual microprocessor chip with 7-bit analog accuracy: Research Articles , 2002 .

[17]  Ángel Rodríguez-Vázquez,et al.  ACE16k: the third generation of mixed-signal SIMD-CNN ACE chips toward VSoCs , 2004, IEEE Transactions on Circuits and Systems I: Regular Papers.

[18]  David A. Patterson,et al.  Computer architecture (2nd ed.): a quantitative approach , 1996 .

[19]  Suleyman Malki Discrete-Time Cellular Neural Networks Implemented on Field-Programmable Gate-Arrays to Build a Virtual Sensor System , 2006 .

[20]  Cheng Wang,et al.  In Search or a Robust Digital CNN System , 2006, 2006 10th International Workshop on Cellular Neural Networks and Their Applications.