Power efficient Networks on Chip

a low power switch design is proposed to achieve power-efficient Network on Chip (NoC). The proposed NoC switch reduces the power consumption of the Butterfly Fat Tree (BFT) architecture by 28 % as compared to the conventional BFT switch. Moreover, the power reduction technique is applied to different NoC architectures. The technique reduces the power consumption of the network by up to 41%. When the power consumption of the whole network including the interswich links and repeaters is taken into account, the overall power consumption is decreased by up to 33% at the maximum operating frequency of the switch. The BFT architecture consumes the minimum power as compared to other NoC architectures.

[1]  W. Dally,et al.  Route packets, not wires: on-chip interconnection networks , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[2]  Partha Pratim Pande,et al.  A scalable communication-centric SoC interconnect architecture , 2004, International Symposium on Signals, Circuits and Systems. Proceedings, SCS 2003. (Cat. No.03EX720).

[3]  Sujit Dey,et al.  An Interconnect Architecture for Networking Systems on Chips , 2002, IEEE Micro.

[4]  Partha Pratim Pande,et al.  Performance evaluation and design trade-offs for network-on-chip interconnect architectures , 2005, IEEE Transactions on Computers.

[5]  Axel Jantsch,et al.  Network on Chip : An architecture for billion transistor era , 2000 .

[6]  A.P. Chandrakasan,et al.  Dual-threshold voltage techniques for low-power digital circuits , 2000, IEEE Journal of Solid-State Circuits.

[7]  Axel Jantsch,et al.  A network on chip architecture and design methodology , 2002, Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002.

[8]  Eby G. Friedman,et al.  Optimum wire sizing of RLC interconnect with repeaters , 2003, GLSVLSI '03.

[9]  Hui-Fen Huang,et al.  Global interconnect width and spacing optimization for latency, bandwidth and power dissipation , 2005, IEEE Transactions on Electron Devices.

[10]  Alain Greiner,et al.  A generic architecture for on-chip packet-switched interconnections , 2000, DATE '00.

[11]  Muhammad M. Khellah,et al.  Power minimization of high-performance submicron CMOS circuits using a dual-Vdd dual-Vth (DVDV) approach , 1999, ISLPED '99.

[12]  M. Elmasry,et al.  Power minimization of high-performance submicron CMOS circuits using a dual-V/sub dd/ dual-V/sub th/ (DVDV) approach , 1999, Proceedings. 1999 International Symposium on Low Power Electronics and Design (Cat. No.99TH8477).

[13]  Partha Pratim Pande,et al.  Design of a switch for network on chip applications , 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..

[14]  Eby G. Friedman,et al.  Sleep switch dual threshold Voltage domino logic with reduced standby leakage current , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[15]  Mohamed A. Abd El-Ghany,et al.  High throughput architecture for high performance NoC , 2009, 2009 IEEE International Symposium on Circuits and Systems.