Low-power filtering via adaptive error-cancellation

A low-power technique for digital filtering referred to as adaptive error-cancellation (AEC) is presented in this paper. The AEC technique falls under the general class of algorithmic noise-tolerance (ANT) techniques proposed earlier for combating transient/soft errors. The proposed AEC technique exploits the correlation between the input and soft errors to estimate and cancel out the latter. In this paper, we apply AEC along with voltage overscaling (VOS), where the voltage is scaled beyond the minimum (referred to as V/sub dd-crit/) necessary for correct operation. We employ the AEC technique in the context of a frequency-division multiplexed (FDM) communication system and demonstrate that up to 71% energy reduction can be achieved over present-day voltage-scaled systems.

[1]  Eiji Fujiwara,et al.  Error-control coding for computer systems , 1989 .

[2]  Naresh R. Shanbhag,et al.  A Mathematical Basis For Power-Reduction In Digital VLSI Systems , 1997 .

[3]  Christer Svensson,et al.  Noise in digital dynamic CMOS circuits , 1994 .

[4]  B. M. Gordon,et al.  Supply and threshold voltage scaling for low power CMOS , 1997, IEEE J. Solid State Circuits.

[5]  P. K. Bondyopadhyay,et al.  Moore's law governs the silicon revolution , 1998, Proc. IEEE.

[6]  Eric A. Vittoz,et al.  Low-power design: ways to approach the limits , 1994, Proceedings of IEEE International Solid-State Circuits Conference - ISSCC '94.

[7]  Farid N. Najm,et al.  Power modeling for high-level power estimation , 2000, IEEE Trans. Very Large Scale Integr. Syst..

[8]  John M. Cioffi,et al.  Very-high-speed digital subscriber lines , 1999, IEEE Commun. Mag..

[9]  Masami Yabusaki,et al.  IMT-2000 standards: network aspects , 1997, IEEE Wirel. Commun..

[10]  Dimitri P. Bertsekas,et al.  Nonlinear Programming , 1997 .

[11]  L. Wang,et al.  Energy-efficiency bounds for noise-tolerant dynamic circuits , 2000, 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353).

[12]  Naresh R. Shanbhag,et al.  Soft digital signal processing , 2001, IEEE Trans. Very Large Scale Integr. Syst..

[13]  Kenneth L. Shepard,et al.  Noise in deep submicron digital design , 1996, Proceedings of International Conference on Computer Aided Design.

[14]  Fumio Watanabe,et al.  IMT-2000 standards: radio aspects , 1997, IEEE Wirel. Commun..

[15]  Naresh R. Shanbhag,et al.  The twin-transistor noise-tolerant dynamic circuit technique , 2001, IEEE J. Solid State Circuits.

[16]  G. Robert Redinbo,et al.  Generalized Algorithm-Based Fault Tolerance: Error Correction via Kalman Estimation , 1998, IEEE Trans. Computers.

[17]  Donatella Sciuto,et al.  An improved fault tolerant architecture at CMOS level , 1997, Proceedings of 1997 IEEE International Symposium on Circuits and Systems. Circuits and Systems in the Information Age ISCAS '97.

[18]  Prithviraj Banerjee,et al.  Fault tolerant VLSI systems , 1993 .

[19]  Naresh R. Shanbhag,et al.  Toward achieving energy efficiency in presence of deep submicron noise , 2000, IEEE Trans. Very Large Scale Integr. Syst..

[20]  S. Haykin,et al.  Adaptive Filter Theory , 1986 .

[21]  Shambhu J. Upadhyaya,et al.  A Comprehensive Reconfiguration Scheme for Fault-Tolerant VLSI/WSI Array Processors , 1997, IEEE Trans. Computers.

[22]  J.E. Mazo,et al.  Digital communications , 1985, Proceedings of the IEEE.

[23]  M. Gagnaire,et al.  An overview of broad-band access technologies , 1997, Proc. IEEE.

[24]  Farid N. Najm,et al.  Statistical Estimation of the Switching Activity in Digital Circuitsy , 1994, 31st Design Automation Conference.

[25]  L. Rabiner,et al.  FIR digital filter design techniques using weighted Chebyshev approximation , 1975, Proceedings of the IEEE.

[26]  Robert H. Dennard,et al.  CMOS scaling for high performance and low power-the next ten years , 1995, Proc. IEEE.

[27]  Naresh R. Shanbhag,et al.  Finite-precision analysis of the pipelined strength-reduced adaptive filter , 1998, IEEE Trans. Signal Process..

[28]  Radu Marculescu,et al.  Sequence compaction for power estimation: theory and practice , 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[29]  A. W. M. van den Enden,et al.  Discrete Time Signal Processing , 1989 .

[30]  Anantha P. Chandrakasan,et al.  Minimizing power consumption in digital CMOS circuits , 1995, Proc. IEEE.

[31]  C. Caraiscos,et al.  A roundoff error analysis of the LMS adaptive algorithm , 1984 .

[32]  Bruce A. Wooley,et al.  A Two's Complement Parallel Array Multiplication Algorithm , 1973, IEEE Transactions on Computers.

[33]  Naresh R. Shanbhag,et al.  Dynamic algorithm transforms for low-power reconfigurable adaptive equalizers , 1999, IEEE Trans. Signal Process..