Si-ULSI with a scaled down future

Semiconductor technology in the 21st century will undergo major changes due to the significant material, engineering, and fundamental limits being approached as a consequence of scaling. Lithography is anticipated to undergo a radical change from optical to nonoptical. Device architecture and interconnects are also expected to undergo major changes in materials, structure, and fabrication technology.

[1]  K. Yamashita,et al.  Shallow source/drain extensions for pMOSFETs with high activation and low process damage fabricated by plasma doping , 1997, International Electron Devices Meeting. IEDM Technical Digest.

[2]  T. Sugii,et al.  A high performance 50 nm PMOSFET using decaborane (B/sub 10/H/sub 14/) ion implantation and 2-step activation annealing process , 1997, International Electron Devices Meeting. IEDM Technical Digest.

[3]  Torres,et al.  Copper Integration In Self Aligned Dual Damascene Architecture , 1997, 1997 Symposium on VLSI Technology.

[4]  T. Shiba,et al.  A raised source/drain technology using in-situ P-doped SiGe and B-doped Si for 0.1-/spl mu/m CMOS ULSIs , 1997, International Electron Devices Meeting. IEDM Technical Digest.

[5]  Soo-Young Oh,et al.  A scaling scheme for interconnect in deep-submicron processes , 1995, Proceedings of International Electron Devices Meeting.

[6]  Y. Hayashi,et al.  A degradation-free Cu/HSQ damascene technology using metal mask patterning and post-CMP cleaning by electrolytic ionized water , 1997, International Electron Devices Meeting. IEDM Technical Digest.

[7]  Yamashita,et al.  Interconnect Scaling Scenario Using A Chip Level Interconnect Model , 1997, 1997 Symposium on VLSI Technology.

[8]  Sugii,et al.  Ultra-thin Ta/sub 2/O/sub 5/SiO/sub 2/ gate insulator with TiN gate technology for 0.1/spl mu/m MOSFETs , 1997, 1997 Symposium on VLSI Technology.

[9]  C. Hu,et al.  Gate Engineering For Performance And Reliability In Deep-submicron CMOS Technology , 1997 .

[10]  Hayashi,et al.  A Robust 0.15/spl mu/m CMOS Technology With CoSi/sub 2/ Salicide And Shallow Trench Isolation , 1997, 1997 Symposium on VLSI Technology.

[11]  Yuan Taur,et al.  CMOS devices below 0.1 /spl mu/m: how high will performance go? , 1997, International Electron Devices Meeting. IEDM Technical Digest.

[12]  P. Roper,et al.  Full copper wiring in a sub-0.25 /spl mu/m CMOS ULSI technology , 1997, International Electron Devices Meeting. IEDM Technical Digest.

[13]  M. Bohr.  Interconnect scaling-the real limiter to high performance ULSI , 1995, Proceedings of International Electron Devices Meeting.

[14]  Oda,et al.  0.6 /spl mu/m Pitlch Highly Reliable Multilevel Interconnection Using Hydrogen Silicate Based Inorganic SOG For Sub-quarter Micron CMOS Technology , 1997, 1997 Symposium on VLSI Technology.

[15]  Integration Of Ultra-low-k Xerogel Gapfill Dielectric For high Performance Sub-o.18 /spl mu/m Interconnects , 1997, 1997 Symposium on VLSI Technology.

[16]  S.C. Sun,et al.  Process technologies for advanced metallization and interconnect systems , 1997, International Electron Devices Meeting. IEDM Technical Digest.

[17]  G.A. Brown,et al.  A comparison of TiN processes for CVD W/TiN gate electrode on 3 nm gate oxide , 1997, International Electron Devices Meeting. IEDM Technical Digest.