High-level hardware design of digital comparator with multiple inputs

Abstract This paper proposes a new method that compares the magnitude between multiple digital input signals and introduces its logic circuit at RTL (register transfer level). For simultaneously comparing multiple inputs, the proposed algorithm uses a simple digital logic function to provide information of the largest (or smallest) value and position for these inputs. The disadvantage of using this method is that it incurs an increase hardware resource usage. To overcome this, we propose a reuse method for the overlapped logic operation. The proposed method focuses on improving the operational clock frequency, in other words, decreasing combinational delay time. After implementing the comparison method with Verilog-HDL (hardware description language), we conduct an experiment with the 28 nm CMOS library provided by TSMC Inc. In the case of 4, 8, 16, and 32 input signals, the proposed method can increase the operating clock frequency by as much as about 1.65, 2.42, 3.28 and 3.45 times, respectively, with about 1.04, 0.97, 1.84 and 4.26 times the hardware resources.

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