Silicon nano-scale devices

In this article, we review our research on electrical transport properties of nano-scale silicon devices at NEC. We used very small devices that were produced by using 10-nm-scale lithographic techniques: electrically variable shallow junction MOSFETs (EJMOSFETs) and lateral hot-electron transistors (LHETs). We succeeded in directly observing the hot-electron current in LHETs and estimated the characteristic length of hot electrons as around 25 nm. Furthermore, we used EJ-MOSFETs to predict that the limit for miniaturization of MOSFETs, in which the source-drain tunneling scheme is applied, is around 5 nm.