Network-on-Chip and Photonic Network-on-Chip Basic Concepts: A Survey

[1]  Ahmad Khademzadeh,et al.  A routing algorithm for reducing optical loss in photonic Networks-on-Chip , 2017, Photonic Network Communications.

[2]  Luca P. Carloni,et al.  Photonic Network-on-Chip Design , 2013, Integrated Circuits and Systems.

[3]  Lin Yang,et al.  A Universal Method for Constructing N-Port Nonblocking Optical Router for Photonic Networks-On-Chip , 2012, Journal of Lightwave Technology.

[4]  Ioannis Tomkos,et al.  Optical Interconnects for Future Data Center Networks , 2012 .

[5]  Ioannis Tomkos,et al.  A Survey on Optical Interconnects for Data Centers , 2012, IEEE Communications Surveys & Tutorials.

[6]  Cheng Li,et al.  Network-on-Chip (NoC) Topologies and Performance: A Review , 2011 .

[7]  Luca P. Carloni,et al.  Physical-Layer Modeling and System-Level Design of Chip-Scale Photonic Interconnection Networks , 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[8]  Luca P. Carloni,et al.  Time-division-multiplexed arbitration in silicon nanophotonic networks-on-chip for high-performance chip multiprocessors , 2011, J. Parallel Distributed Comput..

[9]  Luca P. Carloni,et al.  Circuit-Switched Memory Access in Photonic Interconnection Networks for High-Performance Embedded Computing , 2010, 2010 ACM/IEEE International Conference for High Performance Computing, Networking, Storage and Analysis.

[10]  Wei Zhang,et al.  A Hierarchical Hybrid Optical-Electronic Network-on-Chip , 2010, 2010 IEEE Computer Society Annual Symposium on VLSI.

[11]  Eduardo de la Torre,et al.  Reconfigurable Networks on Chip: DRNoC architecture , 2010, J. Syst. Archit..

[12]  Luca Benini,et al.  Networks on Chips: From research to products , 2010, Design Automation Conference.

[13]  Payman Zarkesh-Ha,et al.  Hybrid network on chip (HNoC): local buses with a global mesh architecture , 2010, SLIP '10.

[14]  Wei Zhang,et al.  Crosstalk noise and bit error rate analysis for optical network-on-chip , 2010, Design Automation Conference.

[15]  S. M. Fakhraie,et al.  Energy/throughput trade-off in a fully asynchronous NoC for GALS-based MPSoC architectures , 2010, 5th International Conference on Design & Technology of Integrated Systems in Nanoscale Era.

[16]  Yu Zhang,et al.  Firefly: illuminating future network-on-chip with nanophotonics , 2009, ISCA '09.

[17]  Leonid Oliker,et al.  Analysis of photonic networks for a chip multiprocessor using scientific applications , 2009, 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip.

[18]  Luca Benini,et al.  SunFloor 3D: A tool for Networks On Chip topology synthesis for 3D systems on chips , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

[19]  Luca P. Carloni,et al.  Photonic Networks-on-Chip for Future Generations of Chip Multiprocessors , 2008, IEEE Transactions on Computers.

[20]  S. Borkar,et al.  An 80-Tile Sub-100-W TeraFLOPS Processor in 65-nm CMOS , 2008, IEEE Journal of Solid-State Circuits.

[21]  Raymond G. Beausoleil,et al.  Nanoelectronic and Nanophotonic Interconnect , 2008, Proceedings of the IEEE.

[22]  Timo Hämäläinen,et al.  On network-on-chip comparison , 2007, 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007).

[23]  Luca P. Carloni,et al.  Photonic NoC for DMA Communications in Chip Multiprocessors , 2007, 15th Annual IEEE Symposium on High-Performance Interconnects (HOTI 2007).

[24]  Luca P. Carloni,et al.  On the Design of a Photonic Network-on-Chip , 2007, First International Symposium on Networks-on-Chip (NOCS'07).

[25]  Tobias Bjerregaard,et al.  A survey of research and practices of Network-on-chip , 2006, CSUR.

[26]  Giuseppe Campobello,et al.  GALS Networks on Chip: A New Solution for Asynchronous Delay-Insensitive Links , 2006, Proceedings of the Design Automation & Test in Europe Conference.

[27]  Chita R. Das,et al.  Impact of virtual channels and adaptive routing on application performance , 2001, SIGCPR '01.

[28]  Ge-Ming Chiu,et al.  The Odd-Even Turn Model for Adaptive Routing , 2000, IEEE Trans. Parallel Distributed Syst..

[29]  Hesam Shabani,et al.  Loss-Aware Router Design Approach for Dimension- Ordered Routing Algorithms in Photonic Networks-on-Chip , 2012 .

[30]  Jong Wu Chan,et al.  Architectural Exploration and Design Methodologies of Photonic Interconnection Networks , 2012 .

[31]  Sao-Jie Chen,et al.  Networks on Chips: Structure and Design Methodologies , 2012, J. Electr. Comput. Eng..

[32]  Gilbert R. Hendry,et al.  Architectures and Design Automation for Photonic Networks On Chip , 2011 .

[33]  Ravi Shankar,et al.  Survey of Network on Chip (NoC) Architectures & Contributions , 2009 .

[34]  Luca Benini,et al.  Networks on Chips : A New SoC Paradigm , 2022 .

[35]  P. Guerrier,et al.  A generic architecture for on-chip packet-switched interconnections , 2000, Proceedings Design, Automation and Test in Europe Conference and Exhibition 2000 (Cat. No. PR00537).

[36]  Wei Zhang,et al.  Formal Worst-case Analysis of Crosstalk Noise in Mesh-based Optical Networks-on-chip , 2022 .