Adaptive Low-Error Fixed-Width Booth Multipliers

In this paper, we propose two 2's-complement fixed-width Booth multipliers that can generate an n-bit product from an n-bit multiplicand and an n-bit multiplier. Compared with previous designs, our multipliers have smaller truncation error, less area, and smaller time delay in the critical paths. A four-step approach is adopted to search for the best error-compensation bias in designing a multiplier suitable for VLSI implementation. Last but not least, we show the superior capability of our designs by inscribing it in a speech signal processor. Simulation results indicate that this novel design surpasses the previous fixed-width Booth multiplier in the precision of the product. An average error reduction of 65–84% compared with a direct-truncation fixed-width multiplier is achieved by adding only a few logic gates.

[1]  Keshab K. Parhi,et al.  Low error fixed-width CSD multiplier with efficient sign extension , 2003, IEEE Trans. Circuits Syst. II Express Briefs.

[2]  E.E. Swartzlander.  Truncated multiplication with approximate rounding , 1999, Conference Record of the Thirty-Third Asilomar Conference on Signals, Systems, and Computers (Cat. No.CH37020).

[3]  Paul M. Embree,et al.  C Language Algorithms for Digital Signal Processing , 1991 .

[4]  Lan-Da Van,et al.  A generalized methodology for lower-error area-efficient fixed-width multipliers , 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

[5]  Shyh-Jye Jou,et al.  Low-error reduced-width Booth multipliers for DSP applications , 2003 .

[6]  Lan-Da Van,et al.  Design of the lower error fixed-width multiplier and its application , 2000 .

[7]  Keshab K. Parhi,et al.  Design of low-error fixed-width modified booth multiplier , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[8]  Sy-Yen Kuo,et al.  A generalized methodology for low-error and area-time efficient fixed-width Booth multipliers , 2004, The 2004 47th Midwest Symposium on Circuits and Systems, 2004. MWSCAS '04..

[9]  Sy-Yen Kuo,et al.  A framework for the design of error-aware power-efficient fixed-width Booth multipliers , 2005, 2005 IEEE International Symposium on Circuits and Systems.