Adapting EPIC Architecture’s Register Stack for Virtual Stack Machines

The register stack (RS) is a major component of the explicit parallel instruction computer (EPIC) architecture. In this paper, our objective is to close the theoretical performance gap between EPIC and stack processors running virtual stack machines - using forth, a simple and canonical stack machine. For this purpose, we first introduce a new calling mechanism using the RS to implement a software-only virtual stack machine. Based upon our performance measurements, we show that the new calling mechanism is a promising technique to improve the performance of stack-based interpretative virtual machines. But limitation in EPIC makes the need for hardware support to reach optimal performance. As a second step, we define an addition to Itanium 2 processor's instruction set to accommodate the new calling mechanism. As our third and last step, we describe a conservative architectural implementation of the extended instruction set