H.264/AVC UHD decoder implementation on multi-cluster platform using hybrid parallelization method

We propose a new hybrid parallelization method for H.264/AVC decoder for UHD (3840×2160) resolution on the proposed multi-clusters platform. We used 4 clusters to decode UHD video application, which cluster is composed of functional partitioned computing elements (1 DSP core and 3 hardware accelerators). The parallelizing efficiency is improved drastically by adopting frame-level parallelization between clusters. Due to the scalable architecture, we can control the number of cluster according to computing requirement. For example, we can use one cluster for FHD video application and four clusters for UHD application. The experimental results show that the parallelism is close to theoretical value by a 1.4–7.6% margin at 2–4 clusters and H.264/AVC UHD decoder runs under 650MHz.

[1]  David A. Patterson,et al.  Computer Architecture - A Quantitative Approach (4. ed.) , 2007 .

[2]  Jong-Tae Kim,et al.  H.264/AVC decoder parallelization and optimization on asymetric multicore platform using dynamic load balancing , 2008, 2008 IEEE International Conference on Multimedia and Expo.

[3]  David A. Patterson,et al.  Computer Architecture: A Quantitative Approach , 1969 .

[4]  Do-Hyung Kim,et al.  High-performance memory interface architecture for high-definition video coding application , 2010, 2010 IEEE International Conference on Image Processing.

[5]  Ki-Seok Chung,et al.  Stage-based frame-partitioned parallelization of H.264/AVC decoding , 2010, IEEE Transactions on Consumer Electronics.

[6]  Ben H. H. Juurlink,et al.  Parallel H.264 Decoding on an Embedded Multicore Processor , 2009, HiPEAC.

[7]  Wang Hongpeng,et al.  Research of parallel decoding algrithm in H.264 on TILE64 , 2009, 2009 2nd IEEE International Conference on Broadband Network & Multimedia Technology.

[8]  Benno Stabernack,et al.  Adaptive multithreaded H.264/AVC decoding , 2009, 2009 Conference Record of the Forty-Third Asilomar Conference on Signals, Systems and Computers.

[9]  Soo-Ik Chae,et al.  Configurable high-performance video platform using multiple RISC clusters connected with separated data and control networks , 2009, 2009 IEEE Workshop on Signal Processing Systems.

[10]  Yong Ho Song,et al.  Efficient coordination of parallel threads of H.264/AVC decoder for performance improvement , 2010, IEEE Transactions on Consumer Electronics.