Localized watermarking: methodology and application to operation scheduling

Recently, a number of techniques for IP protection have been introduced that rely on a selection of a global solution to an optimization problem according to a unique user-specific digital signature. Although such techniques may provide convincing proof of authorship with low hardware overhead, they fail to protect parts of design, do not provide an easy procedure for watermark detection, and are not capable of detecting the watermark when the design or its part is augmented in another larger design. Since these demands are of the highest interest for the IP business, we introduce localized watermarking as an IP protection technique that enables these features while satisfying the demand for low-cost and transparency. We propose a set of protocols that implement the new watermarking methodology at the operation scheduling design level. We have demonstrated that the difficulty of erasing or finding another signature in the synthesized design can be made arbitrarily computationally difficult. The watermarking method has been tested on a set of real-life benchmarks where high likelihood of authorship has been achieved with negligible overhead in solution quality.

[1]  Giovanni De Micheli,et al.  High Level Synthesis of ASlCs un - der Timing and Synchronization Constraints , 1992 .

[2]  Yu-Chin Hsu,et al.  A formal approach to the scheduling problem in high level synthesis , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[3]  Edoardo Charbon Hierarchical watermarking in IC design , 1998, Proceedings of the IEEE 1998 Custom Integrated Circuits Conference (Cat. No.98CH36143).

[4]  David S. Johnson,et al.  Computers and Intractability: A Guide to the Theory of NP-Completeness , 1978 .

[5]  Pierre G. Paulin,et al.  Force-directed scheduling for the behavioral synthesis of ASICs , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[6]  Hugo De Man,et al.  A unified scheduling model for high-level synthesis and code generation , 1995, Proceedings the European Design and Test Conference. ED&TC 1995.

[7]  Miodrag Potkonjak,et al.  Watermarking techniques for intellectual property protection , 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).

[8]  Miodrag Potkonjak,et al.  Media architecture: general purpose vs. multiple application-specific programmable processor , 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).

[9]  Gang Qu,et al.  Analysis of watermarking techniques for graph coloring problem , 1998, 1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287).

[10]  Miodrag Potkonjak,et al.  Robust IP watermarking methodologies for physical design , 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).

[11]  Jason Cong,et al.  Intellectual property protection by watermarking combinational logic synthesis solutions , 1998, ICCAD '98.

[12]  Miodrag Potkonjak,et al.  MediaBench: a tool for evaluating and synthesizing multimedia and communications systems , 1997, Proceedings of 30th Annual International Symposium on Microarchitecture.

[13]  E.A. Lee,et al.  Synchronous data flow , 1987, Proceedings of the IEEE.

[14]  Giovanni De Micheli,et al.  Synthesis and Optimization of Digital Circuits , 1994 .

[15]  Alfred V. Aho,et al.  Data Structures and Algorithms , 1983 .

[16]  Alfred Menezes,et al.  Handbook of Applied Cryptography , 2018 .

[17]  Miodrag Potkonjak,et al.  Fast prototyping of datapath-intensive architectures , 1991, IEEE Design & Test of Computers.

[18]  Scott A. Mahlke,et al.  IMPACT: an architectural framework for multiple-instruction-issue processors , 1991, ISCA '91.

[19]  Miodrag Potkonjak,et al.  Fingerprinting Digital Circuits on Programmable Hardware , 1998, Information Hiding.