A framework and method for hierarchical test generation

The authors have proposed and implemented a dynamic framework and a method for hierarchically generating test patterns from a hierarchical net list. They have shown consistent gains in CPU over the traditional gate-level implementation while maintaining identical levels of fault coverage. In generating and characterizing modules for a large and varied set of hierarchical benchmarks, the authors benefited considerably from the consistent representations that are available during synthesis from a high-level description or when modules are generated by a process of technology mapping into standard cells. The authors introduced the concept of a single generic module which is hierarchical; the traditional AND, OR, NAND, and NOR are included implicitly. They developed a module-oriented decision-making algorithm, MODEM, which entails a dynamic calculus and procedures such as implication, error propagation, line justification, and probabilistic testability measures for a single generic module. Without loss of generality they adapted the control flow and basic features of PODEM in the first implementation of MODEM.<<ETX>>

[1]  Michael H. Schulz,et al.  SOCRATES: a highly efficient automatic test pattern generation system , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[2]  Jacob A. Abraham,et al.  KNOWLEDGE BASED TEST GENERATION FOR VLSI CIRCUITS. , 1987 .

[3]  David Bryan,et al.  Automated synthesis for testability , 1989 .

[4]  Melvin A. Breuer,et al.  Functional Level Primitives in Test Generation , 1980, IEEE Transactions on Computers.

[5]  Füsun Özgüner,et al.  9-V Algorithm for Test Pattern Generation of Combinational Digital Circuits , 1978, IEEE Transactions on Computers.

[6]  John P. Hayes,et al.  Hierarchical test generation using precomputed testsd for modules , 1988, International Test Conference 1988 Proceeding@m_New Frontiers in Testing.

[7]  Peter Muth,et al.  A Nine-Valued Circuit Model for Test Generation , 1976, IEEE Transactions on Computers.

[8]  Janak H. Patel,et al.  A Hierarchical Approach to Test Vector Generation , 1987, 24th ACM/IEEE Design Automation Conference.

[9]  Sheldon B. Akers A Logic System for Fault Test Generation , 1976, IEEE Transactions on Computers.

[10]  Wu-Tung Cheng,et al.  SPLIT circuit model for test generation , 1988, 25th ACM/IEEE, Design Automation Conference.Proceedings 1988..

[11]  M. Ray Mercer,et al.  A Topological Search Algorithm for ATPG , 1987, 24th ACM/IEEE Design Automation Conference.

[12]  Prabhakar Goel,et al.  An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits , 1981, IEEE Transactions on Computers.

[13]  Hideo Fujiwara,et al.  On the Acceleration of Test Generation Algorithms , 1983, IEEE Transactions on Computers.

[14]  Paolo Prinetto,et al.  Testing Strategy and Technique for Macro-Based Circuits , 1985, IEEE Transactions on Computers.

[15]  W. D. Dettloff,et al.  A VLSI fuzzy logic inference engine for real-time process control , 1989, 1989 Proceedings of the IEEE Custom Integrated Circuits Conference.

[16]  J. Paul Roth,et al.  Diagnosis of automata failures: a calculus and a method , 1966 .