Reliability challenges for power devices under active cycling

Power stages are subject to severe stress due to active cycling, resulting in e.g. fast thermal cycling. While some applications require several hundred millions of cycles under normal operation conditions, “disturbances” such as short circuit pose additional challenges. These issues are neither addressed by “classical” silicon wafer technology qualification nor by standard product qualification procedures. Challenges and limitations in applying the principles of Robustness Validation to these issues are discussed.

[1]  M. Stecher,et al.  Influence of inhomogeneous current distribution on the thermal SOA of integrated DMOS transistors , 2004, 2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs.

[2]  Martin Pfost,et al.  Measurement and Simulation of Self-Heating in DMOS Transistors up to Very High Temperatures , 2008, 2008 20th International Symposium on Power Semiconductor Devices and IC's.

[3]  Ivica Manic,et al.  Negative bias temperature instabilities in sequentially stressed and annealed p-channel power VDMOSFETs , 2007, Microelectron. Reliab..

[4]  M. Stecher,et al.  Investigation and Improvement of Fast Temperature-Cycle Reliability for DMOS-Related Conductor Path Design , 2007, 2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual.

[5]  Mauro Ciappa,et al.  Plastic-strain of aluminium interconnections during pulsed operation of IGBT multichip modules , 1996 .

[6]  Michael Glavanovics,et al.  Analysis of wire bond and metallization degradation mechanisms in DMOS power transistors stressed under thermal overload conditions , 2004, Microelectron. Reliab..

[7]  Sebastiano Russo,et al.  Fast thermal fatigue on top metal layer of power devices , 2002, Microelectron. Reliab..

[8]  Michael Goroll,et al.  Exceptional operative gate voltage induces negative bias temperature instability (NBTI) on n-type trench DMOS transistors , 2007, Microelectron. Reliab..

[9]  Geert Van den bosch,et al.  Reliability assessment of integrated power transistors: Lateral DMOS versus vertical DMOS , 2008, Microelectron. Reliab..