论文信息 - VHDL Implementation of AES-128

VHDL Implementation of AES-128

Security has become an increasingly important feature with the growth of electronic communication. The Symmetric in which the same key value is used in both the encryption and decryption calculations are becoming more popular. The AES algorithm is capable of using cryptographic keys of 128, 192, and 256 bits to encrypt and decrypt data in blocks of 128 bits. This standard is based on the Rijndael algorithm. In this project our main concern is to implement all modules of this algorithm on hardware.This methodology uses VHDL implementation of all the modules in terms of Delay

S. R. Biradar | Purnima Gehlot | Richa Sharma

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