A RISCy approach to VLSI

A general trend in computers today is to increase the complexity of architectures along with the increasing potential of implementation technologies. The consequences of this complexity are increased design time, more design errors, inconsistent implementations, and the delay of single chip implementation (Patterson and Ditzel, 1980). The Reduced Instruction Set Computer (RISC) Project investigates a VLSI alternative to this trend. Our initial design is called RISC I. The judicious choice of a small set of the most often used instructions, combined with an architecture tailored to efficient execution of this set, can yield a machine of surprisingly high t h r o u g h p u t . In add i t i on , a s ing l e -ch ip implementation of a simpler machine makes more effective use of limited resources such as the number of transistors, area, and power consumption of present-day VLSI chips (Patterson and S6quin, 1980). Simplicity of the instruction set leads to a small control section, a comparatively short machine cycle, and reduced design cycle time. Students taking part in a multi-term course sequence designed two different nMOS versions of RISC I. The "Gold" group (F i tzpa t r ick , Foderaro , Peek, Peshkess , and Van Dyke) designed a complete 32-bit microprocessor, currently being fabricated. The "Blue" group (Katevenis and Sherburne) started from the same basic organization, but introduced a more sophisticated timing scheme so as to shorten the machine cycle and also reduce chip area. (At present, only the data path of this more ambitious design has been c o m p l e t e d . ) The ch ips were d e s i g n e d us ing on ly "Manhat tan" features with the simple and scalable MeadConway design rules (fabrication lambda=2 microns). When we began to design RISC I, we defined the following goals and constraints: (a) find a reasonable compromise between high performance for high-level language programs and a simple single-chip implementation; (b) make the size of all instructions equal to one word, and execute all instructions in one machine cycle; (c) emphasize register oriented instructions, and (d) restrict memory access to the LOAD and STORE instructions. The resulting architecture has 31 instructions in two formats, uses 32-bit addresses, and supports 8-, 16-, and 32-bit data. The most visible impact of the reduced instruction set is that the area dedicated to cont ro l d r o p p e d f rom 50% (as in typ ica l c o m m e r c i a l