Buffer and router

The embodiment of the invention provides a buffer and a router. The buffer comprises N input ends, N+1 Buffers, an input gating module, a first output gating module, a fault detection module, a scheduling module and a second output gating module. The input gating module is used for gating the entered ith path of input data to one of the N+1 Buffers or to the first output gating module according to an input gating signal transmitted by the scheduling module as for each path of input data entering into the input gating module. The first output gating module is used for simultaneously gating the ith path of input data entering into the first output gating module from the Buffer or the ith path of input data entering into the first output gating module from the input gating module to the fault detection module and the second output gating module according to an output gating signal transmitted by the scheduling module as for each path of input data.