Translation Lookaside Buffer Synchronization in a Multiprocessor System

Most current computer architectures use a high−speed cache to translate user virtual addresses into physical memory addresses. On machines that require software to implement cache fills and invalidations, the software task is fairly straightforward. In a multi−processor multi−cache configuration, however, where processes are allowed to migrate across processors, there is an inherant synchronization problem, as well as performance issues. This paper discusses a solution to these issues that is general enough to implement without specialized hardware, yet offers good performance.