Reducing Reversible Circuit Cost by Adding Lines

Additional lines are required to implement an irreversible function as a reversible circuit. The emphasis, particularly in automated synthesis methods, has been on using the minimal number of additional lines. In this paper, we show that circuit cost reductions can be achieved by adding additional lines. We present an algorithm for line addition that can be targeted to reducing the quantum cost of a circuit or the transistor count for a CMOS implementation. Experimental results show that the cost reduction can be significant even if (1) only a small number of lines (even one) is added and (2) other circuit optimizations have already been applied.

[1]  Yahiko Kambayashi,et al.  Transformation rules for designing CNOT-based quantum circuits , 2002, DAC '02.

[2]  Morteza Saheb Zamani,et al.  A novel synthesis algorithm for reversible circuits , 2007, ICCAD 2007.

[3]  Jing Zhong,et al.  Using Crosspoint Faults in Simplifying Toffoli Networks , 2006, 2006 IEEE North-East Workshop on Circuits and Systems.

[4]  Gerhard W. Dueck,et al.  Reversible cascades with minimal garbage , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[5]  Niraj K. Jha,et al.  Synthesis of reversible logic , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[6]  Morteza Saheb Zamani,et al.  On the Behavior of Substitution-based Reversible Circuit Synthesis Algorithms: Investigation and Improvement , 2007, IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07).

[7]  Gerhard W. Dueck,et al.  A transformation based algorithm for reversible logic synthesis , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

[8]  M. Thornton,et al.  ESOP-based Toffoli Gate Cascade Generation , 2007, 2007 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing.

[9]  Niraj K. Jha,et al.  Reversible logic synthesis with Fredkin and Peres gates , 2008, JETC.

[10]  Robert Wille,et al.  RevLib: An Online Resource for Reversible Functions and Reversible Circuits , 2008, 38th International Symposium on Multiple Valued Logic (ismvl 2008).

[11]  James A. Hutchby,et al.  Limits to binary logic switch scaling - a gedanken model , 2003, Proc. IEEE.

[12]  Gerhard W. Dueck,et al.  Reversible Logic Synthesis , 2020, Reversible and DNA Computing.

[13]  Robert Glück,et al.  Optimized reversible binary-coded decimal adders , 2008, J. Syst. Archit..

[14]  Gerhard W. Dueck,et al.  Quantum circuit simplification using templates , 2005, Design, Automation and Test in Europe.

[15]  Robert Wille,et al.  BDD-based synthesis of reversible logic for large functions , 2009, 2009 46th ACM/IEEE Design Automation Conference.

[16]  Gerhard W. Dueck,et al.  Techniques for the synthesis of reversible Toffoli networks , 2006, TODE.

[17]  Charles H. Bennett,et al.  Logical reversibility of computation , 1973 .

[18]  Alexis De Vos,et al.  A reversible carry-look-ahead adder using control gates , 2002, Integr..

[19]  John P. Hayes,et al.  Synthesis of reversible logic circuits , 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[20]  Thierry Paul,et al.  Quantum computation and quantum information , 2007, Mathematical Structures in Computer Science.

[21]  John P. Hayes,et al.  Reversible logic circuit synthesis , 2002, IWLS.

[22]  R. Landauer,et al.  Irreversibility and heat generation in the computing process , 1961, IBM J. Res. Dev..

[23]  Robert Wille,et al.  Reversible Logic Synthesis with Output Permutation , 2009, 2009 22nd International Conference on VLSI Design.

[24]  Niraj K. Jha,et al.  An Algorithm for Synthesis of Reversible Logic Circuits , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[25]  Barenco,et al.  Elementary gates for quantum computation. , 1995, Physical review. A, Atomic, molecular, and optical physics.

[26]  Robert Wille,et al.  Equivalence Checking of Reversible Circuits , 2009, ISMVL.