Device and Circuit Level Design, Characterization and Implementation of Low Power 7T SRAM Cell using Heterojunction Tunneling Transistors with Oxide Overlap

Abstract The device scaling restricted due to the limitation of the subthreshold swing of the MOS transistor, which is not less than 60 mV/dec. The researchers are concentrating more on power efficient techniques for advanced, more featured, electronic systems. In place of MOS transistor, which is homojunction, if a heterojunction transistor with low bandgap materials used, the subthreshold swing of the transistor being reduce to below 60 mV/decade and low leakage current can obtain. Ge, GeSi, etc. materials are used in the design and implementation Heterojunction Tunneling Transistor (HETT) due to low band gap. In this work, both types of HETTs such as NHETT and PHETT designed and implemented using low bandgap materials with a technique of increasing tunneling area by overlapping. The performance of NHETT and PHETT described by the design and implementation of 7T MOSFET SRAM. The power and delay analysis of this SRAM cell using HETTs presented, and the results compared with MOSFET based standard 6T, conventional 7T SRAM cells.